|
About the Users category
|
|
0
|
70
|
March 20, 2025
|
|
Is This a Forum where I Can Ask Questions about Verilog?
|
|
5
|
79
|
September 1, 2026
|
|
Sanity check: interpreting synth_xilinx BRAM/LUT/FF counts in a memory-topology comparison
|
|
2
|
19
|
August 28, 2026
|
|
An open-source high-level synthesis tool that accepts idiomatic Python
|
|
4
|
124
|
August 20, 2026
|
|
Equiv_opt on hierarchical designs
|
|
1
|
56
|
June 22, 2026
|
|
Why is synth_ecp5 flag `-dff` not enabled by default?
|
|
1
|
82
|
May 20, 2026
|
|
Issue with Defining Power Pins in Standalone Yosys (USE_POWER_PINS not taking effect)
|
|
1
|
63
|
May 15, 2026
|
|
timing closure degraded
|
|
8
|
211
|
May 13, 2026
|
|
Verification of designs involving multiple clocks
|
|
2
|
98
|
April 8, 2026
|
|
Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
|
|
2
|
106
|
March 16, 2026
|
|
Getting 49.15 MHz clock from 3.072 MHz external clock
|
|
1
|
71
|
March 9, 2026
|
|
SRMODE = "CE_OVER_LSR" how to implement in Yosys?
|
|
17
|
221
|
March 5, 2026
|
|
CXXRTL virtual interfaces
|
|
0
|
38
|
March 2, 2026
|
|
What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?
|
|
4
|
111
|
March 1, 2026
|
|
Async2sync and write_aiger -vmap
|
|
2
|
95
|
February 9, 2026
|
|
How do you lint your Yosys Verilog projects?
|
|
4
|
141
|
January 26, 2026
|
|
Setundef doesn't respect selection
|
|
1
|
62
|
January 21, 2026
|
|
Stopping to prevent exponential design size explosion
|
|
2
|
106
|
January 16, 2026
|
|
SBY: liveness check (deadlock / livelock)
|
|
2
|
98
|
December 17, 2025
|
|
Internal pins in Liberty files
|
|
1
|
107
|
December 9, 2025
|
|
Write_json: buffer output after NOT gate left floating
|
|
1
|
71
|
November 19, 2025
|
|
Yosys Formal : VCD Trace Dump
|
|
3
|
118
|
November 12, 2025
|
|
Educational Uses of Open Source EDA Tools
|
|
2
|
163
|
November 4, 2025
|
|
Gate Count Instability from Functionally Equivalent RTL
|
|
1
|
71
|
October 30, 2025
|
|
Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping
|
|
2
|
97
|
October 10, 2025
|
|
Correct method to ignore assert() statements?
|
|
2
|
121
|
October 6, 2025
|
|
Seq #("xx____x_____________") pkt_err (clk, packet_error);
|
|
1
|
70
|
September 28, 2025
|
|
Incremental Synthesis in Yosys
|
|
4
|
126
|
September 9, 2025
|
|
SystemVerilog 2012 Parsing for RVFI
|
|
1
|
93
|
August 31, 2025
|
|
Larger N for input but less time used
|
|
4
|
124
|
August 28, 2025
|