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About the Users category
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0
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43
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March 20, 2025
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Verification of designs involving multiple clocks
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2
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11
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April 8, 2026
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Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
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2
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26
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March 16, 2026
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Getting 49.15 MHz clock from 3.072 MHz external clock
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1
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24
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March 9, 2026
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SRMODE = "CE_OVER_LSR" how to implement in Yosys?
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17
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40
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March 5, 2026
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CXXRTL virtual interfaces
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0
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17
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March 2, 2026
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What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?
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4
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34
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March 1, 2026
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Async2sync and write_aiger -vmap
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2
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28
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February 9, 2026
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How do you lint your Yosys Verilog projects?
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4
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34
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January 26, 2026
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Setundef doesn't respect selection
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1
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15
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January 21, 2026
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Stopping to prevent exponential design size explosion
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2
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64
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January 16, 2026
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SBY: liveness check (deadlock / livelock)
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2
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60
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December 17, 2025
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Internal pins in Liberty files
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1
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33
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December 9, 2025
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Write_json: buffer output after NOT gate left floating
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1
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33
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November 19, 2025
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Yosys Formal : VCD Trace Dump
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3
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47
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November 12, 2025
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Educational Uses of Open Source EDA Tools
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2
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70
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November 4, 2025
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Gate Count Instability from Functionally Equivalent RTL
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1
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34
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October 30, 2025
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Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping
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2
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61
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October 10, 2025
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Correct method to ignore assert() statements?
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2
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73
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October 6, 2025
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Seq #("xx____x_____________") pkt_err (clk, packet_error);
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1
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31
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September 28, 2025
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Incremental Synthesis in Yosys
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4
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88
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September 9, 2025
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SystemVerilog 2012 Parsing for RVFI
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1
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55
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August 31, 2025
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Larger N for input but less time used
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4
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77
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August 28, 2025
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Compiling cv32e40x with SBY
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4
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61
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August 22, 2025
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How to Map Verilog Design Exclusively to Custom Standard Cells in Yosys
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3
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94
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August 19, 2025
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Support for Multiple SMT-LIB expressions
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1
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55
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July 31, 2025
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Support for package import (unexpected TOK_ID)
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3
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89
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July 10, 2025
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Write_firrtl fails
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2
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46
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June 24, 2025
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Filtering internal cell details in nexpnr timing reports
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2
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58
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June 23, 2025
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ICE40 primitives with slang plugin
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1
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76
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June 23, 2025
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