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About the Users category
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0
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67
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March 20, 2025
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Is This a Forum where I Can Ask Questions about Verilog?
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1
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8
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August 14, 2026
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An open-source high-level synthesis tool that accepts idiomatic Python
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3
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85
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July 3, 2026
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Equiv_opt on hierarchical designs
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1
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51
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June 22, 2026
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Why is synth_ecp5 flag `-dff` not enabled by default?
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1
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73
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May 20, 2026
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Issue with Defining Power Pins in Standalone Yosys (USE_POWER_PINS not taking effect)
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1
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62
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May 15, 2026
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timing closure degraded
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8
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203
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May 13, 2026
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Verification of designs involving multiple clocks
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2
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90
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April 8, 2026
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Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
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2
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92
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March 16, 2026
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Getting 49.15 MHz clock from 3.072 MHz external clock
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1
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64
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March 9, 2026
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SRMODE = "CE_OVER_LSR" how to implement in Yosys?
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17
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208
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March 5, 2026
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CXXRTL virtual interfaces
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0
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37
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March 2, 2026
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What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?
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4
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106
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March 1, 2026
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Async2sync and write_aiger -vmap
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2
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85
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February 9, 2026
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How do you lint your Yosys Verilog projects?
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4
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124
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January 26, 2026
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Setundef doesn't respect selection
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1
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59
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January 21, 2026
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Stopping to prevent exponential design size explosion
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2
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99
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January 16, 2026
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SBY: liveness check (deadlock / livelock)
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2
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95
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December 17, 2025
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Internal pins in Liberty files
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1
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87
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December 9, 2025
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Write_json: buffer output after NOT gate left floating
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1
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66
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November 19, 2025
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Yosys Formal : VCD Trace Dump
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3
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113
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November 12, 2025
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Educational Uses of Open Source EDA Tools
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2
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148
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November 4, 2025
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Gate Count Instability from Functionally Equivalent RTL
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1
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68
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October 30, 2025
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Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping
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2
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95
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October 10, 2025
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Correct method to ignore assert() statements?
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2
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115
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October 6, 2025
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Seq #("xx____x_____________") pkt_err (clk, packet_error);
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1
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68
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September 28, 2025
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Incremental Synthesis in Yosys
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4
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122
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September 9, 2025
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SystemVerilog 2012 Parsing for RVFI
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1
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90
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August 31, 2025
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Larger N for input but less time used
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4
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121
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August 28, 2025
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Compiling cv32e40x with SBY
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4
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108
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August 22, 2025
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