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About the Users category
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0
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36
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March 20, 2025
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Internal pins in Liberty files
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0
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3
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December 7, 2025
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Write_json: buffer output after NOT gate left floating
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1
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19
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November 19, 2025
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Yosys Formal : VCD Trace Dump
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3
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28
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November 12, 2025
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Educational Uses of Open Source EDA Tools
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2
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39
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November 4, 2025
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Gate Count Instability from Functionally Equivalent RTL
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1
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21
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October 30, 2025
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Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping
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2
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43
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October 10, 2025
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Correct method to ignore assert() statements?
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2
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45
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October 6, 2025
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Seq #("xx____x_____________") pkt_err (clk, packet_error);
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1
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28
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September 28, 2025
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Incremental Synthesis in Yosys
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4
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69
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September 9, 2025
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SystemVerilog 2012 Parsing for RVFI
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1
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46
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August 31, 2025
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Larger N for input but less time used
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4
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65
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August 28, 2025
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Compiling cv32e40x with SBY
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4
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47
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August 22, 2025
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How to Map Verilog Design Exclusively to Custom Standard Cells in Yosys
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3
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88
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August 19, 2025
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Support for Multiple SMT-LIB expressions
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1
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43
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July 31, 2025
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Support for package import (unexpected TOK_ID)
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3
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76
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July 10, 2025
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Write_firrtl fails
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2
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43
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June 24, 2025
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Filtering internal cell details in nexpnr timing reports
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2
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53
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June 23, 2025
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ICE40 primitives with slang plugin
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1
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72
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June 23, 2025
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Docker Images for oss-cad-suite/etc.?
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3
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54
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June 11, 2025
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Disabling serdes on ECP5UM-5G FPGAs to save power
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0
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67
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June 10, 2025
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SystemVerilog Assertions in Yosys
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1
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138
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June 9, 2025
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General Queries on PLL usage with ECP5
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2
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128
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June 4, 2025
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