Compiling cv32e40x with SBY

Users
1

I am trying to compile cv32e40x, using YOSYS-HQ’s AppNote-123 . I did run make patch, it fails when I try make sby-bmc, pdr or cover.

$ make sby-bmc

SBY 17:16:00 \[cv32e40x_bmc\] base: This license was issued to XXXXXX
SBY 17:16:00 \[cv32e40x_bmc\] base: Customer PoC: XXXXXX
SBY 17:16:01 \[cv32e40x_bmc\] base: VERIFIC-ERROR \[VERI-2326\] AppNote-123/cv32e40x/core-v-verif/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv:208: synthesis of string ‘info_tag’ is not supported
SBY 17:16:01 \[cv32e40x_bmc\] base: VERIFIC-WARNING \[VERI-1209\] AppNote-123/cv32e40x/core-v-verif/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_1p2_assert.sv:223: expression size 6 truncated to fit in target size 5
SBY 17:16:01 \[cv32e40x_bmc\] base: VERIFIC-WARNING \[VERI-1209\] AppNote-123/cv32e40x/core-v-verif/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_1p2_assert.sv:224: expression size 6 truncated to fit in target size 5
SBY 17:16:01 \[cv32e40x_bmc\] base: VERIFIC-WARNING \[VERI-1209\] AppNote-123/cv32e40x/core-v-verif/lib/uvm_agents/uvma_obi_memory/src/uvma_obi_memory_1p2_assert.sv:229: expression size 6 truncated to fit in target size 5
SBY 17:16:01 \[cv32e40x_bmc\] base: ERROR: AppNote-123/cv32e40x/core-v-verif/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv:208: synthesis of string ‘info_tag’ is not supported
SBY 17:16:01 \[cv32e40x_bmc\] base: finished (returncode=1)
SBY 17:16:01 \[cv32e40x_bmc\] base: task failed. ERROR.
SBY 17:16:01 \[cv32e40x_bmc\] summary: Elapsed clock time \[H:MM:SS (secs)\]: 0:00:01 (1)
SBY 17:16:01 \[cv32e40x_bmc\] summary: Elapsed process time \[H:MM:SS (secs)\]: 0:00:01 (1)
SBY 17:16:01 \[cv32e40x_bmc\] summary: engine_0 (smtbmc --keep-going) did not return a status
SBY 17:16:01 \[cv32e40x_bmc\] summary: engine_0 did not produce any traces
SBY 17:16:01 \[cv32e40x_bmc\] DONE (ERROR, rc=16)
SBY 17:16:01 The following tasks failed: \[‘bmc’\]
make: \*\*\* \[Makefile:54: sby-bmc\] Error 16

Error being: SBY 17:16:01 \[cv32e40x_bmc\] base: ERROR: AppNote-123/cv32e40x/core-v-verif/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv:208: synthesis of string ‘info_tag’ is not supported

Are SystemVerilog strings supported by Verific?

Also, this repo was meant to demonstrate using SBY. I am assuming this should have run without issues if I followed the instructions correctly. Am I missing something here?

Happy to provide any more information.
Thank you!

2

That should run without issue, so long as you’re using the version of cva in the makefile. If it isn’t working let me know and I can investigate.

3

Here are the versions that I am using:

AppNote-123/cv32e40x/core-v-verif$ git status
HEAD detached at 7082e9af

/AppNote-123/cv32e40x/core-v-verif/core-v-cores/cv32e40x$ git status
HEAD detached at b658fbe0

These match the versions in the Makefile.

Additonally

$ sby --version
SBY yosys-0.44

make sby-bmc fails with the same error.

Please let me know if you need any more info from me.

Thanks!

4

Thanks, it seems like there was a change in how Verific (or Yosy+Verific) handles strings since that was written. I think previously it was ignored instead of raising an error. I’ve opened a PR for the AppNote which adds the following code to the [script] section:

## Ingore unsynthesized strings
verific -set-info VERI-2326

Alternatively, you could use the following patch to remove the wire:

diff --git a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv
index 1459119f..d8162360 100644
--- a/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv
+++ b/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv
@@ -205,8 +205,6 @@ interface uvma_rvfi_instr_if_t
   logic [CYCLE_CNT_WL-1:0]          cycle_cnt;       // i'th number cycle since reset
   logic [CYCLE_CNT_WL-1:0]          cycle_cnt_q;
 
-  string                            info_tag = "RVFI_INSTR_IF";
-
   logic [(32)-1:0][XLEN-1:0]        gpr_rdata_array;
   logic [(32)-1:0]                  gpr_rmask_array;
   logic [(32)-1:0][XLEN-1:0]        gpr_wdata_array;
@@ -1203,7 +1201,7 @@ function automatic logic[31:0] get_max_exception_cause_f (
   end else if (EXC_CAUSE_LOAD_ACC_FAULT inside {exc_a, exc_b}) begin
       return EXC_CAUSE_LOAD_ACC_FAULT;
   end else begin
-    `uvm_error(info_tag, "unhandled 'max' exception cause");
+    `uvm_error("RVFI_INSTR_IF", "unhandled 'max' exception cause");
     return '0;
   end
 endfunction : get_max_exception_cause_f

If you save that as AppNote-123/cv32e40x/lib.patch, and call git apply ../lib.patch from the core-v-verif directory.

5

Thank you KrystalDelusion! It worked, took a looong time to finish but it worked!

1 Like