Issue with Defining Power Pins in Standalone Yosys (USE_POWER_PINS not taking effect)

Users
1

Hi
I am using Standalone Yosys Version 0.62 for RTL synthesis. In my design, some modules include power pins conditionally using the following Verilog construct:

ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
endif

To enable this, I have added the following in my Yosys script (*.ys file):
verilog_defines -D USE_POWER_PINS

However, the macro does not seem to be taking effect during synthesis, and the power pins are not being included in the design as expected.

Could you please clarify:

  • The correct way to define USE_POWER_PINS in standalone Yosys 0.62

  • Whether verilog_defines is sufficient or if another method is required

  • If there is support for something like NTH_USE_PG_PINS_DEFINES or similar in the Yosys script

    Thanks

2

What frontend are you using to parse your input? verilog_defines only works with read_verilog. You can also usually provide the -D<name> during the read call, e.g. read_verilog -DUSE_POWER_PINS <input.v>. Also make sure that you are calling verilog_defines prior to the relevant read_verilog. I’m not sure what you mean by NTH_USE_PG_PINS_DEFINES?