Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)

Users
1

Using either no definition or 0b00

output states :

ERROR: max frequency for clock is 46.6mhz (FAIL at 48:00 Mhz)

is this a bug? is there a workaround?

seems rather odd, this is very simple code.

SB_HFOSC u_hfosc (
	.CLKHFPU(1'b1),
	.CLKHFEN(1'b1),
	.CLKHF(int_osc)
);

filed as #5751

2

Is your entire design just the HFOSC and you still fail timing? Typically that error is saying the logic part of your design failed to meet timing. What does the reported critical path look like? hmm

3

yup,

I’ve arrived from Radiant, and finding the reporting ‘different’.

I’ll get there.

xx