How do you lint your Yosys Verilog projects?

Users
1

This is a continuation from the discussion here https://github.com/FPGAwars/apio/discussions . Yosys recommends linting with Verilator but when we do so we get from tons of warnings from Yosys standard libraries and with the latest version of Yosys, also fatal errors in a standard ECP5 library.

My questions to you are:

  1. Do you lint the Verilog code of your Yosys projects?
  2. What linter are you using?
  3. If you use Verilator, do you get warnings and errors in Yosys’s libraries and how do you handle them.
2

Yosys recommends linting with Verilator

I don’t think that is strictly accurate:

please do not rely on read_verilog for syntax checking

  • recommend using a simulator (for example Icarus Verilog) or linting with another tool (such as verilator) first
3

Does icarus verilog work better in linting Yosys projects and libraries?

I tried verilator and verible-verilog-lint and they fail.

Regardless of the tool, I think that Yosys should have at least one known good linter that is also be used in Yosys automated testing.

4

FWIW I wasn’t saying that iverilog was better for Yosys, just that we don’t actually have a specific recommended tool.

I also think that is a good idea, so long as it is able to be configured to support the non-standard syntax that is supported by read_verilog.

5

I think that the Yosys team needs to determine if having the ability to ‘lint’ yosys projects is a goal (regardless if it’s done by a third party tool like Verilator or yosys itself), and then go from there.

The approach of ‘yosys doesn’t need to be strict because there are third party lint tools’ and then having yosys projects not being compatible with any lint tool (which is the case since release 2025-10-09) is confusing.