Write_json: buffer output after NOT gate left floating

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1

Hi. I was doing some experiments with yosys and netlistsvg to render a logic schematic from Verilog.
I want to keep the buffers in the schematic, I’m using insbuf (is it the right approach?) and I came across this issue:

// type: sdfrbp 
`timescale 1ns/10ps
`celldefine
module sg13g2_sdfrbp_2 (Q, Q_N, D, SCD, SCE, RESET_B, CLK);
	output Q, Q_N;
	input D, SCD, SCE, RESET_B, CLK;
	
	// Function
	wire int_fwire_d, int_fwire_IQ, int_fwire_IQN;
	wire int_fwire_r, xcr_0;

	ihp_mux2 udp_ihp_mux2(int_fwire_d, D, SCD, SCE);
	not (int_fwire_r, RESET_B);
	ihp_dff_r_err udp_ihp_dff_r_err(xcr_0, CLK, int_fwire_d, int_fwire_r);
	ihp_dff_r udp_ihp_dff_r(int_fwire_IQ, CLK, int_fwire_d, int_fwire_r, xcr_0);
	not (int_fwire_IQN, int_fwire_IQ);
	buf (Q, int_fwire_IQ);
	buf (Q_N, int_fwire_IQN);

endmodule
`endcelldefine


read_verilog sg13g2_sdfrbp_2_functional.v
read_verilog -lib primitives_blackbox.v
hierarchy
prep -top sg13g2_sdfrbp_2
insbuf
write_json sg13g2_sdfrbp_2_functional.json

netlistsvg sg13g2_sdfrbp_2_functional.json -o sg13g2_sdfrbp_2_functional.svg

sg13g2_sdfrbp_2_functional
sg13g2_sdfrbp_2_functional599×270 10.6 KB

Whenever there is a NOT gate before a buffer and an output, the buffer output is left floating. It can be fixed in the json netlist.

A minimal example:

module buftest(
	input A,
	output Z, Z_N);

	wire int_a;
	
	buf buf1(Z, A);
	not not1(int_a, A);
	buf buf2(Z_N, int_a);
	
endmodule

read_verilog buftest.v
prep -top buftest
insbuf
write_json buftest.json

Posting here because I’m not sure if I’m using insbuf correctly, so it might be an user issue. Thanks in advance.

2

You say you want to keep buffers in the schematic, but insbuf will create new buffers in place of direct wire to wire connections. buf is a verilog primitive that never instantiates a $buf cell in Yosys, but will create assignments instead within the frontend. Those assignments probably but not necessarily consistently end up turning to direct wire to wire connections. insbuf will add buffers for all such connections but that will likely add more cells than the number of buf primitives you actually have in your Verilog. Also, prep includes optimization passes which will restructure your design for sure, particularly opt_clean. Yosys isn’t great at delineating what sort of things can be done to a design that avoid structural changes, which is a source of unending frustration. insbuf is an implementation detail, so is whether Verilog buf creates $buf cells or a direct connection. I understand that you’re using Yosys to benefit from its Verilog frontend, but in reality, it’s a synthesis engine at its core, and so it’s likely to do arbitrary changes to your design that preserve functional equivalence

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