Getting 49.15 MHz clock from 3.072 MHz external clock

Users
1

I have hard time understanding PLL as I don’t have experience with FPGA’s. I have 2.822 MHz external clock (I can control pin) and I want to derive 90.32 MHz clock so that they are in sync.

icepll unfortunately says 3.072 MHz is out of range and I don’t know if this means I cannot do it or is this a limitation of tool. Alternative I think is run with 2 clock domains?

2

Ok. Found it is Fin is minimum 10 MHz.