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timing closure degraded
|
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8
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99
|
May 13, 2026
|
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Issue with Defining Power Pins in Standalone Yosys (USE_POWER_PINS not taking effect)
|
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0
|
7
|
May 12, 2026
|
|
RFC: Announcing the new intermediate representation Property IR for assertions (SVA/PSL)
|
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1
|
133
|
May 8, 2026
|
|
SDC support roadmap
|
|
4
|
174
|
May 7, 2026
|
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New PR with up to 2.57x performance improvements
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3
|
71
|
April 27, 2026
|
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Upcoming ABC flow changes
|
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3
|
95
|
April 21, 2026
|
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Verification of designs involving multiple clocks
|
|
2
|
26
|
April 8, 2026
|
|
Non-determinism with OpenROAD
|
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6
|
93
|
March 27, 2026
|
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Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
|
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2
|
32
|
March 16, 2026
|
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Getting 49.15 MHz clock from 3.072 MHz external clock
|
|
1
|
31
|
March 9, 2026
|
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SRMODE = "CE_OVER_LSR" how to implement in Yosys?
|
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17
|
61
|
March 5, 2026
|
|
CXXRTL virtual interfaces
|
|
0
|
20
|
March 2, 2026
|
|
What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?
|
|
4
|
42
|
March 1, 2026
|
|
Src attribute preservation
|
|
1
|
25
|
February 26, 2026
|
|
Default branch changes for nextpnr, icestorm, prjtrellis and prjoxide
|
|
0
|
19
|
February 26, 2026
|
|
Big ideas for the future of Yosys
|
|
0
|
78
|
February 20, 2026
|
|
RFC: SVA / PSL implementation ideas
|
|
3
|
86
|
February 10, 2026
|
|
Consistent source location transfer with Patch
|
|
1
|
42
|
February 9, 2026
|
|
Async2sync and write_aiger -vmap
|
|
2
|
31
|
February 9, 2026
|
|
[Proposal] Automatic test for Yosys cell libraries?
|
|
2
|
51
|
January 26, 2026
|
|
How do you lint your Yosys Verilog projects?
|
|
4
|
41
|
January 26, 2026
|
|
Setundef doesn't respect selection
|
|
1
|
16
|
January 21, 2026
|
|
RFC: Upstreaming a small set of Verific frontend options from silimate fork
|
|
4
|
70
|
January 20, 2026
|
|
Stopping to prevent exponential design size explosion
|
|
2
|
70
|
January 16, 2026
|
|
Flops with parametrized ALOAD aren't optimized and synthesis fails
|
|
5
|
40
|
January 6, 2026
|
|
SBY: liveness check (deadlock / livelock)
|
|
2
|
63
|
December 17, 2025
|
|
Sanitizing by default
|
|
0
|
21
|
December 12, 2025
|
|
Internal pins in Liberty files
|
|
1
|
42
|
December 9, 2025
|
|
RTLIL and Verilog producers and consumers expectations for scopename and hdlname
|
|
1
|
51
|
November 29, 2025
|
|
Multithreading and coverage counters: disable coverage by default?
|
|
2
|
36
|
November 26, 2025
|