|
SRMODE = "CE_OVER_LSR" how to implement in Yosys?
|
|
4
|
12
|
February 20, 2026
|
|
Big ideas for the future of Yosys
|
|
0
|
22
|
February 20, 2026
|
|
RFC: SVA / PSL implementation ideas
|
|
3
|
56
|
February 10, 2026
|
|
Consistent source location transfer with Patch
|
|
1
|
27
|
February 9, 2026
|
|
Async2sync and write_aiger -vmap
|
|
2
|
14
|
February 9, 2026
|
|
[Proposal] Automatic test for Yosys cell libraries?
|
|
2
|
40
|
January 26, 2026
|
|
How do you lint your Yosys Verilog projects?
|
|
4
|
27
|
January 26, 2026
|
|
Setundef doesn't respect selection
|
|
1
|
13
|
January 21, 2026
|
|
RFC: Upstreaming a small set of Verific frontend options from silimate fork
|
|
4
|
58
|
January 20, 2026
|
|
Stopping to prevent exponential design size explosion
|
|
2
|
57
|
January 16, 2026
|
|
Flops with parametrized ALOAD aren't optimized and synthesis fails
|
|
5
|
33
|
January 6, 2026
|
|
SBY: liveness check (deadlock / livelock)
|
|
2
|
55
|
December 17, 2025
|
|
Sanitizing by default
|
|
0
|
20
|
December 12, 2025
|
|
Internal pins in Liberty files
|
|
1
|
29
|
December 9, 2025
|
|
RTLIL and Verilog producers and consumers expectations for scopename and hdlname
|
|
1
|
46
|
November 29, 2025
|
|
Multithreading and coverage counters: disable coverage by default?
|
|
2
|
33
|
November 26, 2025
|
|
SDC support roadmap
|
|
3
|
118
|
November 20, 2025
|
|
Write_json: buffer output after NOT gate left floating
|
|
1
|
32
|
November 19, 2025
|
|
Yosys Formal : VCD Trace Dump
|
|
3
|
43
|
November 12, 2025
|
|
Handling non-const pointer fields and pointer-like structure fields when making const RTLIL objects thread-safe
|
|
0
|
20
|
November 10, 2025
|
|
Replacing json11?
|
|
1
|
35
|
November 7, 2025
|
|
Fixing `IdString` refcounting
|
|
9
|
114
|
November 5, 2025
|
|
Educational Uses of Open Source EDA Tools
|
|
2
|
60
|
November 4, 2025
|
|
Adding gmock to test dependencies
|
|
3
|
52
|
November 1, 2025
|
|
Gate Count Instability from Functionally Equivalent RTL
|
|
1
|
27
|
October 30, 2025
|
|
Cleaning up log sinks
|
|
2
|
62
|
October 21, 2025
|
|
Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping
|
|
2
|
58
|
October 10, 2025
|
|
gowin:Mapping DSP cells (MULT36x36, MULT18x18 and MULT9x9) during synthesis
|
|
2
|
38
|
October 7, 2025
|
|
Correct method to ignore assert() statements?
|
|
2
|
59
|
October 6, 2025
|
|
Parallel OptMergePass implementation
|
|
17
|
154
|
October 6, 2025
|