|
An open-source high-level synthesis tool that accepts idiomatic Python
|
|
3
|
28
|
July 3, 2026
|
|
Equiv_opt on hierarchical designs
|
|
1
|
39
|
June 22, 2026
|
|
Adding support for LATCH mapping to `dfflibmap`
|
|
1
|
21
|
June 22, 2026
|
|
Consistent source location transfer with Patch
|
|
3
|
123
|
June 11, 2026
|
|
Fixing `IdString` refcounting
|
|
11
|
172
|
June 11, 2026
|
|
An update on C++-ification of logging APIs
|
|
5
|
113
|
June 9, 2026
|
|
Poll: LLMs - quality, morality, opportunity, policy
|
|
2
|
121
|
May 29, 2026
|
|
Proving the prover, or "How do we verify we're constructing SVA assertions correctly?"
|
|
3
|
166
|
May 29, 2026
|
|
Why is synth_ecp5 flag `-dff` not enabled by default?
|
|
1
|
59
|
May 20, 2026
|
|
RFC: Announcing the new intermediate representation Property IR for assertions (SVA/PSL)
|
|
4
|
302
|
May 18, 2026
|
|
Itp engine: fixpoint convergence and skip parameter
|
|
0
|
67
|
May 15, 2026
|
|
Issue with Defining Power Pins in Standalone Yosys (USE_POWER_PINS not taking effect)
|
|
1
|
60
|
May 15, 2026
|
|
timing closure degraded
|
|
8
|
193
|
May 13, 2026
|
|
SDC support roadmap
|
|
4
|
239
|
May 7, 2026
|
|
New PR with up to 2.57x performance improvements
|
|
3
|
144
|
April 27, 2026
|
|
Upcoming ABC flow changes
|
|
3
|
169
|
April 21, 2026
|
|
Verification of designs involving multiple clocks
|
|
2
|
76
|
April 8, 2026
|
|
Non-determinism with OpenROAD
|
|
6
|
178
|
March 27, 2026
|
|
Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
|
|
2
|
89
|
March 16, 2026
|
|
Getting 49.15 MHz clock from 3.072 MHz external clock
|
|
1
|
59
|
March 9, 2026
|
|
SRMODE = "CE_OVER_LSR" how to implement in Yosys?
|
|
17
|
207
|
March 5, 2026
|
|
CXXRTL virtual interfaces
|
|
0
|
35
|
March 2, 2026
|
|
What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?
|
|
4
|
99
|
March 1, 2026
|
|
Src attribute preservation
|
|
1
|
74
|
February 26, 2026
|
|
Default branch changes for nextpnr, icestorm, prjtrellis and prjoxide
|
|
0
|
50
|
February 26, 2026
|
|
Big ideas for the future of Yosys
|
|
0
|
103
|
February 20, 2026
|
|
RFC: SVA / PSL implementation ideas
|
|
3
|
116
|
February 10, 2026
|
|
Async2sync and write_aiger -vmap
|
|
2
|
84
|
February 9, 2026
|
|
[Proposal] Automatic test for Yosys cell libraries?
|
|
2
|
98
|
January 26, 2026
|
|
How do you lint your Yosys Verilog projects?
|
|
4
|
107
|
January 26, 2026
|