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Equiv_opt on hierarchical designs
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1
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25
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June 22, 2026
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Adding support for LATCH mapping to `dfflibmap`
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1
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10
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June 22, 2026
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Consistent source location transfer with Patch
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3
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111
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June 11, 2026
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Fixing `IdString` refcounting
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11
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164
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June 11, 2026
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An update on C++-ification of logging APIs
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5
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107
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June 9, 2026
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Poll: LLMs - quality, morality, opportunity, policy
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2
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111
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May 29, 2026
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Proving the prover, or "How do we verify we're constructing SVA assertions correctly?"
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3
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145
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May 29, 2026
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Why is synth_ecp5 flag `-dff` not enabled by default?
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1
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51
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May 20, 2026
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RFC: Announcing the new intermediate representation Property IR for assertions (SVA/PSL)
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4
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284
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May 18, 2026
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Itp engine: fixpoint convergence and skip parameter
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0
|
60
|
May 15, 2026
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Issue with Defining Power Pins in Standalone Yosys (USE_POWER_PINS not taking effect)
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1
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51
|
May 15, 2026
|
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timing closure degraded
|
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8
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183
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May 13, 2026
|
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SDC support roadmap
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4
|
227
|
May 7, 2026
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New PR with up to 2.57x performance improvements
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3
|
130
|
April 27, 2026
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Upcoming ABC flow changes
|
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3
|
154
|
April 21, 2026
|
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Verification of designs involving multiple clocks
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|
2
|
70
|
April 8, 2026
|
|
Non-determinism with OpenROAD
|
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6
|
160
|
March 27, 2026
|
|
Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
|
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2
|
80
|
March 16, 2026
|
|
Getting 49.15 MHz clock from 3.072 MHz external clock
|
|
1
|
54
|
March 9, 2026
|
|
SRMODE = "CE_OVER_LSR" how to implement in Yosys?
|
|
17
|
173
|
March 5, 2026
|
|
CXXRTL virtual interfaces
|
|
0
|
31
|
March 2, 2026
|
|
What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?
|
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4
|
87
|
March 1, 2026
|
|
Src attribute preservation
|
|
1
|
63
|
February 26, 2026
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|
Default branch changes for nextpnr, icestorm, prjtrellis and prjoxide
|
|
0
|
46
|
February 26, 2026
|
|
Big ideas for the future of Yosys
|
|
0
|
101
|
February 20, 2026
|
|
RFC: SVA / PSL implementation ideas
|
|
3
|
110
|
February 10, 2026
|
|
Async2sync and write_aiger -vmap
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|
2
|
76
|
February 9, 2026
|
|
[Proposal] Automatic test for Yosys cell libraries?
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|
2
|
92
|
January 26, 2026
|
|
How do you lint your Yosys Verilog projects?
|
|
4
|
90
|
January 26, 2026
|
|
Setundef doesn't respect selection
|
|
1
|
49
|
January 21, 2026
|