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Proving the prover, or "How do we verify we're constructing SVA assertions correctly?"
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0
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4
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May 15, 2026
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RFC: Announcing the new intermediate representation Property IR for assertions (SVA/PSL)
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2
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154
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May 15, 2026
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Issue with Defining Power Pins in Standalone Yosys (USE_POWER_PINS not taking effect)
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1
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14
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May 15, 2026
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timing closure degraded
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8
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107
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May 13, 2026
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SDC support roadmap
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4
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177
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May 7, 2026
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New PR with up to 2.57x performance improvements
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3
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75
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April 27, 2026
|
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Upcoming ABC flow changes
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3
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97
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April 21, 2026
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Verification of designs involving multiple clocks
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2
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28
|
April 8, 2026
|
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Non-determinism with OpenROAD
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6
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96
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March 27, 2026
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Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
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2
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32
|
March 16, 2026
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Getting 49.15 MHz clock from 3.072 MHz external clock
|
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1
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32
|
March 9, 2026
|
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SRMODE = "CE_OVER_LSR" how to implement in Yosys?
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17
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62
|
March 5, 2026
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CXXRTL virtual interfaces
|
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0
|
21
|
March 2, 2026
|
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What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?
|
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4
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43
|
March 1, 2026
|
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Src attribute preservation
|
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1
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25
|
February 26, 2026
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Default branch changes for nextpnr, icestorm, prjtrellis and prjoxide
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0
|
19
|
February 26, 2026
|
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Big ideas for the future of Yosys
|
|
0
|
81
|
February 20, 2026
|
|
RFC: SVA / PSL implementation ideas
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3
|
87
|
February 10, 2026
|
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Consistent source location transfer with Patch
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1
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43
|
February 9, 2026
|
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Async2sync and write_aiger -vmap
|
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2
|
31
|
February 9, 2026
|
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[Proposal] Automatic test for Yosys cell libraries?
|
|
2
|
52
|
January 26, 2026
|
|
How do you lint your Yosys Verilog projects?
|
|
4
|
42
|
January 26, 2026
|
|
Setundef doesn't respect selection
|
|
1
|
16
|
January 21, 2026
|
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RFC: Upstreaming a small set of Verific frontend options from silimate fork
|
|
4
|
71
|
January 20, 2026
|
|
Stopping to prevent exponential design size explosion
|
|
2
|
71
|
January 16, 2026
|
|
Flops with parametrized ALOAD aren't optimized and synthesis fails
|
|
5
|
40
|
January 6, 2026
|
|
SBY: liveness check (deadlock / livelock)
|
|
2
|
64
|
December 17, 2025
|
|
Sanitizing by default
|
|
0
|
22
|
December 12, 2025
|
|
Internal pins in Liberty files
|
|
1
|
43
|
December 9, 2025
|
|
RTLIL and Verilog producers and consumers expectations for scopename and hdlname
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|
1
|
53
|
November 29, 2025
|