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Yosys Formal : VCD Trace Dump
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1
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8
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November 8, 2025
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Replacing json11?
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1
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16
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November 7, 2025
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Fixing `IdString` refcounting
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9
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74
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November 5, 2025
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Educational Uses of Open Source EDA Tools
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2
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27
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November 4, 2025
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Adding gmock to test dependencies
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3
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40
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November 1, 2025
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Gate Count Instability from Functionally Equivalent RTL
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1
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12
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October 30, 2025
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Cleaning up log sinks
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2
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49
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October 21, 2025
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SDC support roadmap
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2
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59
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October 13, 2025
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Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping
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2
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36
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October 10, 2025
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gowin:Mapping DSP cells (MULT36x36, MULT18x18 and MULT9x9) during synthesis
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2
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18
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October 7, 2025
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Correct method to ignore assert() statements?
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2
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44
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October 6, 2025
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Parallel OptMergePass implementation
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17
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99
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October 6, 2025
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Quoted strings in pass arguments
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4
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60
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October 6, 2025
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Seq #("xx____x_____________") pkt_err (clk, packet_error);
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1
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27
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September 28, 2025
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Announcing the RTLIL MLIR dialect for CIRCT
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1
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81
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September 22, 2025
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Cleaning up `log_id()` and `RTLIL::unescape_id()`
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2
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32
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September 17, 2025
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Faster RTLIL Parser
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6
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98
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September 16, 2025
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Making usage of `RTLIL::IdString` more efficient
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6
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59
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September 9, 2025
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An update on C++-ification of logging APIs
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3
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51
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September 9, 2025
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Incremental Synthesis in Yosys
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4
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63
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September 9, 2025
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Fixing `RTLIL::Const`
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3
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36
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September 5, 2025
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PSA: LLVM21 on macOS is failing Yosys builds
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0
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27
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September 1, 2025
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SystemVerilog 2012 Parsing for RVFI
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1
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45
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August 31, 2025
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Larger N for input but less time used
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4
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63
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August 28, 2025
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Compiling cv32e40x with SBY
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4
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47
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August 22, 2025
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How to Map Verilog Design Exclusively to Custom Standard Cells in Yosys
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3
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88
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August 19, 2025
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Support for Multiple SMT-LIB expressions
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1
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42
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July 31, 2025
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Support for package import (unexpected TOK_ID)
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3
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72
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July 10, 2025
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Write_firrtl fails
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2
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41
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June 24, 2025
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Filtering internal cell details in nexpnr timing reports
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2
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49
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June 23, 2025
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