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Is This a Forum where I Can Ask Questions about Verilog?
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2
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19
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August 16, 2026
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Your CMake workflows
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1
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47
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July 23, 2026
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An open-source high-level synthesis tool that accepts idiomatic Python
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3
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86
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July 3, 2026
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Equiv_opt on hierarchical designs
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1
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51
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June 22, 2026
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Adding support for LATCH mapping to `dfflibmap`
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1
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31
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June 22, 2026
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Consistent source location transfer with Patch
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3
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140
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June 11, 2026
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Fixing `IdString` refcounting
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11
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176
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June 11, 2026
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An update on C++-ification of logging APIs
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5
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118
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June 9, 2026
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Poll: LLMs - quality, morality, opportunity, policy
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2
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173
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May 29, 2026
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Proving the prover, or "How do we verify we're constructing SVA assertions correctly?"
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3
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197
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May 29, 2026
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Why is synth_ecp5 flag `-dff` not enabled by default?
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1
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73
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May 20, 2026
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RFC: Announcing the new intermediate representation Property IR for assertions (SVA/PSL)
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4
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326
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May 18, 2026
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Itp engine: fixpoint convergence and skip parameter
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0
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71
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May 15, 2026
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Issue with Defining Power Pins in Standalone Yosys (USE_POWER_PINS not taking effect)
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1
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62
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May 15, 2026
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timing closure degraded
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8
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204
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May 13, 2026
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SDC support roadmap
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4
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262
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May 7, 2026
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New PR with up to 2.57x performance improvements
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3
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148
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April 27, 2026
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Upcoming ABC flow changes
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3
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197
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April 21, 2026
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Verification of designs involving multiple clocks
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2
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90
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April 8, 2026
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Non-determinism with OpenROAD
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6
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186
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March 27, 2026
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Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
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2
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93
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March 16, 2026
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Getting 49.15 MHz clock from 3.072 MHz external clock
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1
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64
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March 9, 2026
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SRMODE = "CE_OVER_LSR" how to implement in Yosys?
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17
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208
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March 5, 2026
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CXXRTL virtual interfaces
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0
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37
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March 2, 2026
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What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?
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4
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106
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March 1, 2026
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Src attribute preservation
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1
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76
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February 26, 2026
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Default branch changes for nextpnr, icestorm, prjtrellis and prjoxide
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0
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53
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February 26, 2026
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Big ideas for the future of Yosys
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0
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111
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February 20, 2026
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RFC: SVA / PSL implementation ideas
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3
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120
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February 10, 2026
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Async2sync and write_aiger -vmap
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2
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85
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February 9, 2026
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