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Internal pins in Liberty files
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0
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3
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December 7, 2025
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RTLIL and Verilog producers and consumers expectations for scopename and hdlname
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1
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31
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November 29, 2025
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Multithreading and coverage counters: disable coverage by default?
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2
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25
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November 26, 2025
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SDC support roadmap
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3
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91
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November 20, 2025
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Write_json: buffer output after NOT gate left floating
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1
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19
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November 19, 2025
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Yosys Formal : VCD Trace Dump
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3
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28
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November 12, 2025
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Handling non-const pointer fields and pointer-like structure fields when making const RTLIL objects thread-safe
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0
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12
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November 10, 2025
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Replacing json11?
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1
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28
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November 7, 2025
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Fixing `IdString` refcounting
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9
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87
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November 5, 2025
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Educational Uses of Open Source EDA Tools
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2
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39
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November 4, 2025
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Adding gmock to test dependencies
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3
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45
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November 1, 2025
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Gate Count Instability from Functionally Equivalent RTL
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1
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21
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October 30, 2025
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Cleaning up log sinks
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2
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57
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October 21, 2025
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Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping
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2
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43
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October 10, 2025
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gowin:Mapping DSP cells (MULT36x36, MULT18x18 and MULT9x9) during synthesis
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2
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22
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October 7, 2025
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Correct method to ignore assert() statements?
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2
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45
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October 6, 2025
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Parallel OptMergePass implementation
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17
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122
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October 6, 2025
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Quoted strings in pass arguments
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4
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60
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October 6, 2025
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Seq #("xx____x_____________") pkt_err (clk, packet_error);
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1
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28
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September 28, 2025
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Announcing the RTLIL MLIR dialect for CIRCT
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1
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83
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September 22, 2025
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Cleaning up `log_id()` and `RTLIL::unescape_id()`
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2
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42
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September 17, 2025
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Faster RTLIL Parser
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6
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104
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September 16, 2025
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Making usage of `RTLIL::IdString` more efficient
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6
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61
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September 9, 2025
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An update on C++-ification of logging APIs
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3
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53
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September 9, 2025
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Incremental Synthesis in Yosys
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4
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69
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September 9, 2025
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Fixing `RTLIL::Const`
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3
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39
|
September 5, 2025
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PSA: LLVM21 on macOS is failing Yosys builds
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0
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27
|
September 1, 2025
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SystemVerilog 2012 Parsing for RVFI
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1
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46
|
August 31, 2025
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Larger N for input but less time used
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4
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65
|
August 28, 2025
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Compiling cv32e40x with SBY
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4
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47
|
August 22, 2025
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