|
Consistent source location transfer with Patch
|
|
4
|
191
|
October 15, 2026
|
|
Interactive schematic viewer and netlist analysis plugin for yosys
|
|
0
|
22
|
October 7, 2026
|
|
Dropping macOS x86-64 wheels
|
|
1
|
27
|
October 5, 2026
|
|
Adding a pass for Multiple Constant Multiplication (mcm)
|
|
6
|
157
|
September 21, 2026
|
|
Reverse-engineering Renesas ForgeFPGA SLG47910V for open-source Yosys/FPGA support
|
|
0
|
38
|
September 11, 2026
|
|
Is This a Forum where I Can Ask Questions about Verilog?
|
|
5
|
116
|
September 1, 2026
|
|
Interim LLM Policy
|
|
0
|
67
|
August 31, 2026
|
|
Sanity check: interpreting synth_xilinx BRAM/LUT/FF counts in a memory-topology comparison
|
|
2
|
25
|
August 28, 2026
|
|
An open-source high-level synthesis tool that accepts idiomatic Python
|
|
4
|
151
|
August 20, 2026
|
|
Your CMake workflows
|
|
1
|
78
|
July 23, 2026
|
|
Equiv_opt on hierarchical designs
|
|
1
|
59
|
June 22, 2026
|
|
Adding support for LATCH mapping to `dfflibmap`
|
|
1
|
45
|
June 22, 2026
|
|
Fixing `IdString` refcounting
|
|
11
|
183
|
June 11, 2026
|
|
An update on C++-ification of logging APIs
|
|
5
|
125
|
June 9, 2026
|
|
Poll: LLMs - quality, morality, opportunity, policy
|
|
2
|
235
|
May 29, 2026
|
|
Proving the prover, or "How do we verify we're constructing SVA assertions correctly?"
|
|
3
|
225
|
May 29, 2026
|
|
Why is synth_ecp5 flag `-dff` not enabled by default?
|
|
1
|
87
|
May 20, 2026
|
|
RFC: Announcing the new intermediate representation Property IR for assertions (SVA/PSL)
|
|
4
|
412
|
May 18, 2026
|
|
Itp engine: fixpoint convergence and skip parameter
|
|
0
|
81
|
May 15, 2026
|
|
Issue with Defining Power Pins in Standalone Yosys (USE_POWER_PINS not taking effect)
|
|
1
|
64
|
May 15, 2026
|
|
timing closure degraded
|
|
8
|
228
|
May 13, 2026
|
|
SDC support roadmap
|
|
4
|
305
|
May 7, 2026
|
|
New PR with up to 2.57x performance improvements
|
|
3
|
178
|
April 27, 2026
|
|
Upcoming ABC flow changes
|
|
3
|
262
|
April 21, 2026
|
|
Verification of designs involving multiple clocks
|
|
2
|
115
|
April 8, 2026
|
|
Non-determinism with OpenROAD
|
|
6
|
199
|
March 27, 2026
|
|
Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
|
|
2
|
124
|
March 16, 2026
|
|
Getting 49.15 MHz clock from 3.072 MHz external clock
|
|
1
|
72
|
March 9, 2026
|
|
SRMODE = "CE_OVER_LSR" how to implement in Yosys?
|
|
17
|
246
|
March 5, 2026
|
|
CXXRTL virtual interfaces
|
|
0
|
38
|
March 2, 2026
|