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New PR with up to 2.57x performance improvements
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3
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35
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April 27, 2026
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Upcoming ABC flow changes
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3
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83
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April 21, 2026
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timing closure degraded
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5
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48
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April 19, 2026
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Verification of designs involving multiple clocks
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2
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25
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April 8, 2026
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Non-determinism with OpenROAD
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6
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88
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March 27, 2026
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Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
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2
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31
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March 16, 2026
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Getting 49.15 MHz clock from 3.072 MHz external clock
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1
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29
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March 9, 2026
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SRMODE = "CE_OVER_LSR" how to implement in Yosys?
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17
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49
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March 5, 2026
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CXXRTL virtual interfaces
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0
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19
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March 2, 2026
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What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?
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4
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40
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March 1, 2026
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Src attribute preservation
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1
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22
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February 26, 2026
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Default branch changes for nextpnr, icestorm, prjtrellis and prjoxide
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0
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17
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February 26, 2026
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Big ideas for the future of Yosys
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0
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74
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February 20, 2026
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RFC: SVA / PSL implementation ideas
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3
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76
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February 10, 2026
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Consistent source location transfer with Patch
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1
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38
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February 9, 2026
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Async2sync and write_aiger -vmap
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2
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30
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February 9, 2026
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[Proposal] Automatic test for Yosys cell libraries?
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2
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50
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January 26, 2026
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How do you lint your Yosys Verilog projects?
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4
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39
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January 26, 2026
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Setundef doesn't respect selection
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1
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15
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January 21, 2026
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RFC: Upstreaming a small set of Verific frontend options from silimate fork
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4
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69
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January 20, 2026
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Stopping to prevent exponential design size explosion
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2
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69
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January 16, 2026
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Flops with parametrized ALOAD aren't optimized and synthesis fails
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5
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38
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January 6, 2026
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SBY: liveness check (deadlock / livelock)
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2
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62
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December 17, 2025
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Sanitizing by default
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0
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20
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December 12, 2025
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Internal pins in Liberty files
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1
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38
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December 9, 2025
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RTLIL and Verilog producers and consumers expectations for scopename and hdlname
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1
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48
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November 29, 2025
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Multithreading and coverage counters: disable coverage by default?
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2
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36
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November 26, 2025
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SDC support roadmap
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3
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159
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November 20, 2025
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Write_json: buffer output after NOT gate left floating
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1
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36
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November 19, 2025
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Yosys Formal : VCD Trace Dump
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3
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52
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November 12, 2025
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