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Allow library build as cmake project
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0
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7
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October 20, 2026
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Consistent source location transfer with Patch
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4
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206
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October 15, 2026
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Interactive schematic viewer and netlist analysis plugin for yosys
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0
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25
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October 7, 2026
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Dropping macOS x86-64 wheels
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1
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30
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October 5, 2026
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Adding a pass for Multiple Constant Multiplication (mcm)
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6
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168
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September 21, 2026
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Reverse-engineering Renesas ForgeFPGA SLG47910V for open-source Yosys/FPGA support
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0
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40
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September 11, 2026
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Is This a Forum where I Can Ask Questions about Verilog?
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5
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117
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September 1, 2026
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Interim LLM Policy
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0
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69
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August 31, 2026
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Sanity check: interpreting synth_xilinx BRAM/LUT/FF counts in a memory-topology comparison
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2
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26
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August 28, 2026
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An open-source high-level synthesis tool that accepts idiomatic Python
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4
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157
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August 20, 2026
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Your CMake workflows
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1
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80
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July 23, 2026
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Equiv_opt on hierarchical designs
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1
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62
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June 22, 2026
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Adding support for LATCH mapping to `dfflibmap`
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1
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45
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June 22, 2026
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Fixing `IdString` refcounting
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11
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183
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June 11, 2026
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An update on C++-ification of logging APIs
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5
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126
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June 9, 2026
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Poll: LLMs - quality, morality, opportunity, policy
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2
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238
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May 29, 2026
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Proving the prover, or "How do we verify we're constructing SVA assertions correctly?"
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3
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226
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May 29, 2026
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Why is synth_ecp5 flag `-dff` not enabled by default?
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1
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88
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May 20, 2026
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RFC: Announcing the new intermediate representation Property IR for assertions (SVA/PSL)
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4
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419
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May 18, 2026
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Itp engine: fixpoint convergence and skip parameter
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0
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82
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May 15, 2026
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Issue with Defining Power Pins in Standalone Yosys (USE_POWER_PINS not taking effect)
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1
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65
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May 15, 2026
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timing closure degraded
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8
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230
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May 13, 2026
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SDC support roadmap
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4
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306
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May 7, 2026
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New PR with up to 2.57x performance improvements
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3
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182
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April 27, 2026
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Upcoming ABC flow changes
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3
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265
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April 21, 2026
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Verification of designs involving multiple clocks
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2
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116
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April 8, 2026
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Non-determinism with OpenROAD
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6
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199
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March 27, 2026
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Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
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2
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126
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March 16, 2026
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Getting 49.15 MHz clock from 3.072 MHz external clock
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1
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73
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March 9, 2026
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SRMODE = "CE_OVER_LSR" how to implement in Yosys?
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17
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246
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March 5, 2026
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