Async2sync and write_aiger -vmap

[Truito]

Hi, I am using async2sync command and write_aiger with the vmap option on verilog netlists.

The obtained mapping is as I would have expected. Except for the latches that comes from the async2sync pass. Where I got stuff like that:

latch 0 0 $abc$307160$auto$async2sync.cc:234:execute$10130
latch 0 0 $auto$async2sync.cc:234:execute$10130
latch 1 0 $abc$307160$auto$async2sync.cc:234:execute$10128
latch 1 0 $auto$async2sync.cc:234:execute$10128
latch 2 0 $abc$307160$auto$async2sync.cc:234:execute$10126
latch 2 0 $auto$async2sync.cc:234:execute$10126
latch 3 0 $abc$307160$auto$async2sync.cc:234:execute$10124
latch 3 0 $auto$async2sync.cc:234:execute$10124
latch 4 0 $abc$307160$auto$async2sync.cc:234:execute$10122
latch 4 0 $auto$async2sync.cc:234:execute$10122

Which are hard to trace back to the original netlist.

Is there any option, when using async2sync, to track from which registers in the original netlist these latches come from or to understand these characters eg. some of the numbers in the string might help to understand the mapping ?

Best,

Félix

[widlarizer]

I opened a bug report for this, since it’s undesirable behavior and could be fixed

async2sync doesn't copy src attributes consistently

There’s also related upcoming work that should eliminate these problems across the board:

Consistent source location transfer with Patch

The greatest source of loss of source attributes is synthesis with abc, but not all users use abc and there’s a lot of gaps in Yosys passes. To address this, there’s two major features I think we need. Patch I have started prototyping a data structure called Patch that allows passes to prepare rewrites to the design and that will come with automatic source transfer. Potential future benefits is higher functional clarity, lower reliance on opt_clean to garbage collect design objects and cheaper …

[Truito]

Nice, thanks a lot !