SRMODE = "CE_OVER_LSR" how to implement in Yosys?

Users
1

FD1P3XZ my_reg [7:0] {

.D(),

.SP(),

.CK(),

.SR(),

.Q(),

}

regarding SR type latches I found:

However, this did not provide immediate relief!!

The above snippet builds (UP5K) on Lattice Radiant, under Yosys reports:

Can’t find object for defparam my_reg

I moved to Yosys some years ago, just happened to avoid needing to use this.

Migrating Icecube2 to Radiant references: FD1P3XZ primitive instantiation

2

You’ve got a couple of options and you aren’t being very specific.

Inference

The doc you link says that you can either “let the synthesis infer register functions from the source RTL”. That should work well for synchronous flops, and unfortunately not as well yet for asynchronous. I have some code for improving asynchronous flip flop inference that hasn’t been integrated yet.

Track asynchronous flip flop improvements here:

Instantiating Yosys-internal cells

The docs page you’re linking is about the “word-level” register cells. For single-bit but technology-unspecific cells, there’s this page:

The cell types $_SDFFCE_[NP][NP][01][NP]_ implement d-type flip-flops with synchronous reset and enable, with enable having priority over reset

From there you could either directly instantiate the Yosys-internal $_SDFFCE_... type that corresponds to the polarities you want.

Instantiating iCEcube2 style cells

You can see in this file that those kinds of cells map to ice40-specific cells SB_DFFE... and SB_DFFNE.... Their behavioral models are here. These are apparently iCEcube2 names for these primitives. Yosys “knows” these ice40-specific cell types, so you might want to use those instead.

Instantiating Radiant style cells

Yosys can’t resolve FD1P3XZ with parameters, it doesn’t know what that is. The doc you link even suggests you should instead instantiate FD1P3IZ or whatever, which doesn’t need parameters. Instantiating that and adding an empty FD1P3IZ module (this causes it to be interpreted as a “blackbox”) should work too.

I think we could turn this reply of mine into an application note at this point…

3

Hi widlarizer, many thanks for the prompt and lengthy response.

I’ve attached the complete module, it comes from a project provided by Lattice, and I have no idea how to follow your guide, and would be grateful, if further instruction was available.

Whether this module could contribute to the application note I cannot say.

Thank you once again!

module ice40_resetn(
input clk,
output resetn
);

wire [7:0] cnt;
wire [7:0] cnt_in;
wire cnt_en;
wire r_resetn;

FD1P3XZ u_cnt_reg [7:0] (
.D(cnt_in),
.SP(cnt_en),
.CK(clk),
.SR(1’b0),
.Q(cnt));
defparam u_cnt_reg[7].REGSET = “RESET”;
defparam u_cnt_reg[6].REGSET = “RESET”;
defparam u_cnt_reg[5].REGSET = “RESET”;
defparam u_cnt_reg[4].REGSET = “RESET”;
defparam u_cnt_reg[3].REGSET = “RESET”;
defparam u_cnt_reg[2].REGSET = “RESET”;
defparam u_cnt_reg[1].REGSET = “RESET”;
defparam u_cnt_reg[0].REGSET = “RESET”;
defparam u_cnt_reg[7].SRMODE = “CE_OVER_LSR”;
defparam u_cnt_reg[6].SRMODE = “CE_OVER_LSR”;
defparam u_cnt_reg[5].SRMODE = “CE_OVER_LSR”;
defparam u_cnt_reg[4].SRMODE = “CE_OVER_LSR”;
defparam u_cnt_reg[3].SRMODE = “CE_OVER_LSR”;
defparam u_cnt_reg[2].SRMODE = “CE_OVER_LSR”;
defparam u_cnt_reg[1].SRMODE = “CE_OVER_LSR”;
defparam u_cnt_reg[0].SRMODE = “CE_OVER_LSR”;

FD1P3XZ u_r_resetn0 (
.D(1’b1 ),
.SP(!cnt_en),
.CK(clk),
.SR(1’b0),
.Q(r_resetn));
defparam u_r_resetn0.REGSET = “RESET”;
defparam u_r_resetn0.SRMODE = “CE_OVER_LSR”;

assign resetn = r_resetn;
assign cnt_in = cnt + 8’d1;
assign cnt_en = (cnt != 8’hff);

endmodule

4

It’s up to you to know what sort of flip flop you want, not up to me to guess. If it’s not your Verilog, but from Lattice, ask Lattice. Looking up “FD1P3XZ” including the quotes on Google finds nothing that would define what it’s supposed to do with what sort of parameter

There’s no point in feeding code nobody understands into Yosys or any other tool

5

Many thanks, chasing…

6

I wrote to the author asking about FD1P3XZ he replied to me: “You can use any old flop for this…”

tx

1 Like
7

Hi widlarizer,

regarding: Instantiating that and adding an empty FD1P3IZ module (this causes it to be interpreted as a “blackbox”) should work too.

FD1P3DZ wfm in Radiant without parameters.

When building with Yosys, I added an empty module named FD1P3DZ,

however error FD1P3DZ does not have a port named ‘Q’ is output.

else if the ports are included FD1P3DZ is not supported.

what did I not understand?

I did not find any example of any use in verilog in the wild, including github

Thank you again

8

When adding an empty module it should still have the correct ports, just not have any implementation (anything after the port definition). e.g.

module FD1S3IX(input CD, D, CK, output Q);
endmodule
9

Hi KrystalDelusion,

thanks, I’m using

module FD1P3DZ(input D, CK, SP, CD, output Q);
endmodule

whilst FD1P3DZ builds under Radiant, under Yosys response is “unsupported”

I did not find .sp as port, but something similar (enable port) is needed, I tried E without luck

10

Can you provide a minimal reproducer showing your problem?

11

This module builds and does the necessary under Radiant:

module ice40_resetn(
input clk,
output resetn
);

wire [7:0] cnt;
wire [7:0] cnt_in;
wire cnt_en;
wire r_resetn;

FD1P3DZ u_cnt_reg [7:0](
.D (cnt_in),//I: data in
.CK (clk), //I: clock input
.SP (cnt_en),//ce);
.CD (1’b0),//I: sync reset input
.Q (cnt)//O: data out
);

FD1P3DZ u_r_resetn0 (
.D (1’b1), //I: data in
.CK (clk), //I: clock input
.SP (!cnt_en),//ce);
.CD (1’b0),//I: sync reset input
.Q (r_resetn)//O: data out
);

assign resetn = r_resetn;
assign cnt_in = cnt + 8’d1;
assign cnt_en = (cnt != 8’hff);

endmodule

I have tried adding various blank modules, but none build under Yosys, so far

12 
read_verilog << EOT
module FD1P3DZ (input D, CK, SP, CD, output Q);
endmodule

module ice40_resetn(
input clk,
output resetn
);

wire [7:0] cnt;
wire [7:0] cnt_in;
wire cnt_en;
wire r_resetn;

FD1P3DZ u_cnt_reg [7:0](
.D (cnt_in),//I: data in
.CK (clk), //I: clock input
.SP (cnt_en),//ce);
.CD (1'b0),//I: sync reset input
.Q (cnt)//O: data out
);

FD1P3DZ u_r_resetn0 (
.D (1'b1), //I: data in
.CK (clk), //I: clock input
.SP (!cnt_en),//ce);
.CD (1'b0),//I: sync reset input
.Q (r_resetn)//O: data out
);

assign resetn = r_resetn;
assign cnt_in = cnt + 8'd1;
assign cnt_en = (cnt != 8'hff);

endmodule
EOT

synth_ice40 -device u -top ice40_resetn

works fine with Yosys 0.61

13

Thank you so much, however on my system Yosys 0.61+21 output is

ERROR: cell type ‘FD1P3DZ’ is unsupported (instantiated as ‘VII.u_resetn.u_cnt_reg[5]’)

0 warnings 1 error

make: *** [Makefile:12: top.asc] error 255

Copied and pasted to avoid typos.

yosys -p 'synth_ice40 -json top.json’

How to proceed? UP5K SG48

14

Does the code I included work for you?

15

It does not, but I switched to using always@.

16

Can you post a log file with the error?

17

That’s a nextpnr error, not yosys. You only asked about yosys. You can use iCEcube2 style cells instead as I suggested, I checked and nextpnr seems to understand only SB_DFF* style cells for ice40. FD1P3BX, FD1P3DX, FD1P3IX, FD1P3JX are supported for the nexus familiy

18

Emil,

that’s really kind, in a bit deep for me, but good for the search trail

thank you

xx