|
[Proposal] Automatic test for Yosys cell libraries?
|
|
2
|
99
|
January 26, 2026
|
|
How do you lint your Yosys Verilog projects?
|
|
4
|
125
|
January 26, 2026
|
|
Setundef doesn't respect selection
|
|
1
|
59
|
January 21, 2026
|
|
RFC: Upstreaming a small set of Verific frontend options from silimate fork
|
|
4
|
141
|
January 20, 2026
|
|
Stopping to prevent exponential design size explosion
|
|
2
|
101
|
January 16, 2026
|
|
Flops with parametrized ALOAD aren't optimized and synthesis fails
|
|
5
|
111
|
January 6, 2026
|
|
SBY: liveness check (deadlock / livelock)
|
|
2
|
96
|
December 17, 2025
|
|
Sanitizing by default
|
|
0
|
60
|
December 12, 2025
|
|
Internal pins in Liberty files
|
|
1
|
88
|
December 9, 2025
|
|
RTLIL and Verilog producers and consumers expectations for scopename and hdlname
|
|
1
|
108
|
November 29, 2025
|
|
Multithreading and coverage counters: disable coverage by default?
|
|
2
|
83
|
November 26, 2025
|
|
Write_json: buffer output after NOT gate left floating
|
|
1
|
66
|
November 19, 2025
|
|
Yosys Formal : VCD Trace Dump
|
|
3
|
113
|
November 12, 2025
|
|
Handling non-const pointer fields and pointer-like structure fields when making const RTLIL objects thread-safe
|
|
0
|
57
|
November 10, 2025
|
|
Replacing json11?
|
|
1
|
91
|
November 7, 2025
|
|
Educational Uses of Open Source EDA Tools
|
|
2
|
150
|
November 4, 2025
|
|
Adding gmock to test dependencies
|
|
3
|
95
|
November 1, 2025
|
|
Gate Count Instability from Functionally Equivalent RTL
|
|
1
|
68
|
October 30, 2025
|
|
Cleaning up log sinks
|
|
2
|
82
|
October 21, 2025
|
|
Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping
|
|
2
|
95
|
October 10, 2025
|
|
gowin:Mapping DSP cells (MULT36x36, MULT18x18 and MULT9x9) during synthesis
|
|
2
|
114
|
October 7, 2025
|
|
Correct method to ignore assert() statements?
|
|
2
|
118
|
October 6, 2025
|
|
Parallel OptMergePass implementation
|
|
17
|
261
|
October 6, 2025
|
|
Quoted strings in pass arguments
|
|
4
|
119
|
October 6, 2025
|
|
Seq #("xx____x_____________") pkt_err (clk, packet_error);
|
|
1
|
70
|
September 28, 2025
|
|
Announcing the RTLIL MLIR dialect for CIRCT
|
|
1
|
172
|
September 22, 2025
|
|
Cleaning up `log_id()` and `RTLIL::unescape_id()`
|
|
2
|
85
|
September 17, 2025
|
|
Faster RTLIL Parser
|
|
6
|
181
|
September 16, 2025
|
|
Making usage of `RTLIL::IdString` more efficient
|
|
6
|
116
|
September 9, 2025
|
|
Incremental Synthesis in Yosys
|
|
4
|
123
|
September 9, 2025
|