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[Proposal] Automatic test for Yosys cell libraries?
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2
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99
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January 26, 2026
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How do you lint your Yosys Verilog projects?
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4
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125
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January 26, 2026
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Setundef doesn't respect selection
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1
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59
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January 21, 2026
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RFC: Upstreaming a small set of Verific frontend options from silimate fork
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4
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140
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January 20, 2026
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Stopping to prevent exponential design size explosion
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2
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100
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January 16, 2026
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Flops with parametrized ALOAD aren't optimized and synthesis fails
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5
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110
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January 6, 2026
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SBY: liveness check (deadlock / livelock)
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2
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96
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December 17, 2025
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Sanitizing by default
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0
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60
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December 12, 2025
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Internal pins in Liberty files
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1
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87
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December 9, 2025
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RTLIL and Verilog producers and consumers expectations for scopename and hdlname
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1
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107
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November 29, 2025
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Multithreading and coverage counters: disable coverage by default?
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2
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81
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November 26, 2025
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Write_json: buffer output after NOT gate left floating
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1
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66
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November 19, 2025
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Yosys Formal : VCD Trace Dump
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3
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113
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November 12, 2025
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Handling non-const pointer fields and pointer-like structure fields when making const RTLIL objects thread-safe
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0
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57
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November 10, 2025
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Replacing json11?
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1
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89
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November 7, 2025
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Educational Uses of Open Source EDA Tools
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2
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148
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November 4, 2025
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Adding gmock to test dependencies
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3
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95
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November 1, 2025
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Gate Count Instability from Functionally Equivalent RTL
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1
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68
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October 30, 2025
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Cleaning up log sinks
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2
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79
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October 21, 2025
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Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping
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2
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95
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October 10, 2025
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gowin:Mapping DSP cells (MULT36x36, MULT18x18 and MULT9x9) during synthesis
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2
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111
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October 7, 2025
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Correct method to ignore assert() statements?
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2
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115
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October 6, 2025
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Parallel OptMergePass implementation
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17
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260
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October 6, 2025
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Quoted strings in pass arguments
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4
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119
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October 6, 2025
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Seq #("xx____x_____________") pkt_err (clk, packet_error);
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1
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68
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September 28, 2025
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Announcing the RTLIL MLIR dialect for CIRCT
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1
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168
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September 22, 2025
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Cleaning up `log_id()` and `RTLIL::unescape_id()`
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2
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85
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September 17, 2025
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Faster RTLIL Parser
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6
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179
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September 16, 2025
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Making usage of `RTLIL::IdString` more efficient
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6
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115
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September 9, 2025
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Incremental Synthesis in Yosys
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4
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122
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September 9, 2025
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