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Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)
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2
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137
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March 16, 2026
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SRMODE = "CE_OVER_LSR" how to implement in Yosys?
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17
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249
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March 5, 2026
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CXXRTL virtual interfaces
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0
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40
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March 2, 2026
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What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?
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4
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132
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March 1, 2026
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Src attribute preservation
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1
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101
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February 26, 2026
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Default branch changes for nextpnr, icestorm, prjtrellis and prjoxide
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0
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67
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February 26, 2026
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Big ideas for the future of Yosys
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0
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128
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February 20, 2026
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RFC: SVA / PSL implementation ideas
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3
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131
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February 10, 2026
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Async2sync and write_aiger -vmap
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2
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107
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February 9, 2026
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[Proposal] Automatic test for Yosys cell libraries?
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2
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111
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January 26, 2026
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How do you lint your Yosys Verilog projects?
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4
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175
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January 26, 2026
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Setundef doesn't respect selection
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1
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68
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January 21, 2026
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RFC: Upstreaming a small set of Verific frontend options from silimate fork
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4
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163
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January 20, 2026
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Stopping to prevent exponential design size explosion
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2
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135
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January 16, 2026
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Flops with parametrized ALOAD aren't optimized and synthesis fails
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5
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160
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January 6, 2026
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SBY: liveness check (deadlock / livelock)
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2
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102
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December 17, 2025
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Sanitizing by default
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0
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70
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December 12, 2025
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Internal pins in Liberty files
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1
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128
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December 9, 2025
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RTLIL and Verilog producers and consumers expectations for scopename and hdlname
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1
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116
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November 29, 2025
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Multithreading and coverage counters: disable coverage by default?
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2
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97
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November 26, 2025
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Write_json: buffer output after NOT gate left floating
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1
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79
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November 19, 2025
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Yosys Formal : VCD Trace Dump
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3
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132
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November 12, 2025
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Handling non-const pointer fields and pointer-like structure fields when making const RTLIL objects thread-safe
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0
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60
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November 10, 2025
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Replacing json11?
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1
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113
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November 7, 2025
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Educational Uses of Open Source EDA Tools
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2
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185
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November 4, 2025
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Adding gmock to test dependencies
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3
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103
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November 1, 2025
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Gate Count Instability from Functionally Equivalent RTL
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1
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78
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October 30, 2025
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Cleaning up log sinks
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2
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87
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October 21, 2025
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Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping
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2
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106
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October 10, 2025
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gowin:Mapping DSP cells (MULT36x36, MULT18x18 and MULT9x9) during synthesis
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2
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156
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October 7, 2025
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