zapta
January 25, 2026, 4:33pm
1
Background:
Yosys recommends linting projects with Verilator and the oss-cad-suite package includes a Verilator binary. https://github.com/YosysHQ/yosys/blob/main/README.md#additional-information
Yosys standard libraries throw tons of warnings with linting a project, requiring the user to create Verilator rule suppression file.
This PR synth_ecp5 and synth_nexus to synth_lattice by mmicko · Pull Request #3908 · YosysHQ/yosys · GitHub from October 2025 broke the ECP5 linting completely with a fatal error and it’s broken since then.
Desired goals
Yosys projects pass Verilator lints with no errors and warnings due to the standard libraries.
The standard libraries are subjects to automatic tests such that any breakage is detected before merging a PR.
Before getting into a plan proposal, is there an interest from the Yosys’s maintainer for contributions in this direction?
(I am the main maintainer of Apio and as such the one that has to deal with breakages of the ‘apio lint’ command and hacking around the standard libraries issues)
I think having the Yosys shared libraries not raise warnings is preferable, and not raising errors is desirable. But also Yosys does explicitly support non standard syntax which should be included in any such checks.
zapta
January 26, 2026, 10:43pm
3
I posted here an example that shows the lint that is broken since oct 2025. With this proposal it would be flagged immediately by a test.
opened 06:13PM - 26 Jan 26 UTC
enhancement
### Version
Yosys 0.61+56 (git sha1 f5ea73eb9-dirty, aarch64-apple-darwin23.5-c… lang++ 18.1.8 -fPIC -O3)
### On which OS did this happen?
macOS
### Reproduction Steps
(Discussion on the subject here https://github.com/YosysHQ/yosys/discussions/5633)
This regression was caused by this PR https://github.com/YosysHQ/yosys/pull/3908/files that changed the ECP5 libraries.
With an ECP5 project, run something like
```
verilator_bin --lint-only --quiet --bbox-unsup --timing \
-Wno-TIMESCALEMOD -Wno-MULTITOP -DAPIO_SIM=0 \
--top-module ledon \
-I/Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5 \
_rules.vlt \
/Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5/cells_sim.v
/Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5/cells_bb.v \
ledon.v
```
### Expected Behavior
Linting complete successfuly with no fatal errors (exit code 0)
### Actual Behavior
Fatal errors and non zero exit code.
```
%Error: /Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5/cells_bb.v:4:13: syntax error, unexpected '.', expecting '['
4 | module GSR (...);
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=5.041 for more assistance.
%Error: /Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5/cells_bb.v:9:13: syntax error, unexpected '.', expecting '['
9 | module PUR (...);
| ^
%Error: /Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5/cells_bb.v:11:5: syntax error, unexpected input
11 | input PUR;
| ^~~~~
%Error: /Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5/cells_bb.v:15:14: syntax error, unexpected '.', expecting '['
15 | module SGSR (...);
| ^
%Error: /Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5/cells_bb.v:21:18: syntax error, unexpected '.', expecting '['
21 | module PDPW16KD (...);
| ^
%Error: /Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5/cells_bb.v:97:5: syntax error, unexpected input
97 | input DI35;
| ^~~~~
%Error: /Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5/cells_bb.v:211:20: syntax error, unexpected '.', expecting '['
211 | module MULT18X18D (...);
| ^
%Error: /Users/user/Downloads/oss-cad-suite-2026-01-24/share/yosys/ecp5/cells_bb.v:237:5: syntax error, unexpected input
237 | input A17;
|
```