The greatest source of loss of source attributes is synthesis with abc, but not all users use abc and there’s a lot of gaps in Yosys passes. To address this, there’s two major features I think we need.
Patch
I have started prototyping a data structure called Patch that allows passes to prepare rewrites to the design and that will come with automatic source transfer. Potential future benefits is higher functional clarity, lower reliance on opt_clean to garbage collect design objects and cheaper equivalence checking of pass runs
Twines
To manage larger amounts of src locations, including “fused” source locations (some cells and wires are derived from multiple places in the source code) I’ll be adding new twine-tree data types which requires changes to the RTLIL textual format. This should improve performance and memory efficiency beyond the status quo, but extending the RTLIL textual format is something we should release only once we’re happy with it
Development will have to happen in PRs targeting the emil/src-location-story feature branch due to being fairly severe additions to infrastructure and publicly exposed interfaces. After it’s merged to main, I plan on keeping Patch an unstable feature, so that external users have access to it with appropriate expectations about it being likely to evolve for some time.
I’m putting up this thread with the sparse information I have right now just so I have something to point to, and major changes to the plan still might happen. I’ve also had to focus on other tasks for a couple of weeks so I haven’t touched it in a while