How do you lint your Yosys Verilog projects?

[zapta]

Does icarus verilog work better in linting Yosys projects and libraries?

I tried verilator and verible-verilog-lint and they fail.

Regardless of the tool, I think that Yosys should have at least one known good linter that is also be used in Yosys automated testing.

[Proposal] Automatic test for Yosys cell libraries?

Background: Yosys recommends linting projects with Verilator and the oss-cad-suite package includes a Verilator binary. https://github.com/YosysHQ/yosys/blob/main/README.md#additional-information Yosys standard libraries throw tons of warnings with linting a project, requiring the user to create Verilator rule suppression file. This PR synth_ecp5 and synth_nexus to synth_lattice by mmicko · Pull Request #3908 · YosysHQ/yosys · GitHub from October 2025 broke the ECP5 linting completely with a f…