Hi everyone,
I am trying to synthesize my Verilog design in Yosys so that it maps exclusively to my custom standard cells. I have already modified my .lib file to include only my custom cells, but when I run synthesis, Yosys still uses built-in AND/OR cells. When I remove those built-in cells entirely from the .lib , the mapping process fails.
I have two universal combinational cell that can implement any logic function, and for sequential logic I plan to use the same cells with a flip-flop and asynchronous clear. My goal is to have Yosys use only these cells for the synthesis without introducing any other combinational cells.(one of cells is attached)
Are you able to share the script you are trying to run?
There is an example on the documentation for mapping to cell libraries.
yes, these pictures are lib file and my scripts.
there is no AND/OR/NOT cell in my lib file .
For future reference, please use the code block features instead of images of code, like so:
read_verilog my_design.v
# Check hierarchy
hierarchy -check -top top_level
This can be done with the </> symbol in the editor, pressing “ctrl+E”, or using triple backticks in the markdown editor:
```
this is a code block
```
In regards to your question, as far as I understand it ABC is not capable of mapping to cells if it can’t drive all the inputs. As a quick test I modified the cell library in the counter example from the documentation, replacing the NOR gate with one which takes 3 inputs worked fine, but replacing it with one which takes 4 inputs meant the NOR gate was no longer able to be used (and removing the NAND gate caused the mapping to fail).
One solution could be to use the extract pass; you could use abc to map to the component parts of your cells (such as a mux, or a mux with an or gate on the select), and then use extract to find groups of those components to combine together. Any leftover cells can then be mapped to individual cells with techmap.
