Support for package import (unexpected TOK_ID)

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1

Hello, I am trying to compile an SV module that imports packages defined separately.
i.e cache_ctl_pkg.sv has

package cache_ctl_pkg;
  parameter MAIN_MEM_ADDRESS_WIDTH = 10;
  parameter BIT_DEPTH = 3; 
endpackage: cache_ctl_pkg

fifo_rtl.sv has:

import cache_ctl_pkg::*;
typedef logic [MAIN_MEM_ADDRESS_WIDTH-1 : 0] word_t;
typedef word_t [0 : (2**BIT_DEPTH-1)] buffer_t;

When compiling with yosys(with TabbyCAD license), I get this
fifo_rtl.sv:1: ERROR: syntax error, unexpected TOK_ID

I tried looking it up but could not find much if Yosys does/not support Wildcard import.

Any help in pointing out what I maybe doing wrong would be of great help. Thanks!

2

You mentioned TabbyCAD, but that looks like an error from read_verilog. What is the script you’re using to load the design?

3

I have TabbyCAD License, but before running any verification with sby, I am just trying to compile in yosys with read_verilog.

Here is how I am trying to compile it:
I have just the two .sv files in a directory (fifo_rtl.sv, cache_ctl_pkg.sv)

After loading yosys:

yosys> read_verilog -sv *.sv

1. Executing Verilog-2005 frontend: cache_ctl_pkg.sv
Parsing SystemVerilog input from `cache_ctl_pkg.sv' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: fifo_rtl.sv
Parsing SystemVerilog input from `fifo_rtl.sv' to AST representation.
fifo_rtl.sv:1: ERROR: syntax error, unexpected TOK_ID

I also tried compiling just the top file(fifo_rtl.sv)

yosys> read_verilog -sv fifo_rtl.sv

1. Executing Verilog-2005 frontend: fifo_rtl.sv
Parsing SystemVerilog input from `fifo_rtl.sv' to AST representation.
fifo_rtl.sv:1: ERROR: syntax error, unexpected TOK_ID

Am I doing it correctly? Please let me know if I am missing something here. At the moment my interest is in compiling the design in Yosys, run simulation and then move to verification aspects later on. I am facing issues in compiling the design. This is the snippet where it fails.

Some info about my Yosys install:

⦗Tabby CAD Suite⦘ *** $ yosys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite -- YosysHQ Edition [202408060857]     |
 |  Copyright (C) 2012 - 2024 YosysHQ GmbH                                    |
 |  For support, please contact support@yosyshq.com                           |
 \----------------------------------------------------------------------------/
 Yosys 0.44 (git sha1 80ba43d26, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

Happy to provide any more information. Thank you!

4

You need to first read the file which declares the package, and then the file which uses the package; but I think the read_verilog frontend doesn’t support the import keyword and you would have to use cache_ctl_pkg::MAIN_MEM_ADDRESS_WIDTH etc to reference things in the package.

Alternatively, since you have the TabbyCAD Suite, you can use the Verific front end to load the SystemVerilog instead, which does support import. You can do that with read instead of read_verilog (which will fall back to using read_verilog if verific is unavailable), or by explicitly calling verific -sv cache_ctl_pkg.sv fifo_rtl.sv.

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