| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| Fixing `RTLIL::Const` |
|
3 | 75 | September 5, 2025 |
| PSA: LLVM21 on macOS is failing Yosys builds |
|
0 | 57 | September 1, 2025 |
| SystemVerilog 2012 Parsing for RVFI |
|
1 | 90 | August 31, 2025 |
| Larger N for input but less time used |
|
4 | 121 | August 28, 2025 |
| Compiling cv32e40x with SBY |
|
4 | 110 | August 22, 2025 |
| How to Map Verilog Design Exclusively to Custom Standard Cells in Yosys |
|
3 | 133 | August 19, 2025 |
| Support for Multiple SMT-LIB expressions |
|
1 | 82 | July 31, 2025 |
| Support for package import (unexpected TOK_ID) |
|
3 | 149 | July 10, 2025 |
| Write_firrtl fails |
|
2 | 86 | June 24, 2025 |
| Filtering internal cell details in nexpnr timing reports |
|
2 | 109 | June 23, 2025 |
| ICE40 primitives with slang plugin |
|
1 | 107 | June 23, 2025 |
| Docker Images for oss-cad-suite/etc.? |
|
3 | 114 | June 11, 2025 |
| Disabling serdes on ECP5UM-5G FPGAs to save power |
|
0 | 98 | June 10, 2025 |
| SystemVerilog Assertions in Yosys |
|
1 | 288 | June 9, 2025 |
| General Queries on PLL usage with ECP5 |
|
2 | 203 | June 4, 2025 |