Hi YosysHQ team,
I’m currently working on reverse-engineering the Renesas ForgeFPGA SLG47910V architecture, used by the Vicharak Shrike family, with the goal of enabling a more open-source FPGA toolchain.
I’m starting from the bitstreams generated by the vendor toolchain and using controlled designs and P&R experiments to correlate the generated configuration data with the underlying FPGA architecture. So far I’ve been investigating logic/routing resources, I/O placement, and particularly the dedicated clock architecture and clock-tree configuration.
I also have an experimental Apio flow working end-to-end on real Shrike-Fi hardware using Yosys → Renesas eda-placer → bitstream generation → ESP32-S3 programming.
The longer-term goal is to understand the architecture and configuration format sufficiently to develop an open-source P&R/nextpnr backend.
I’d be interested in any advice from the Yosys/FPGA community on the best way to structure the Yosys-side architecture and any existing work or related efforts I should be aware of.
I can share reverse-engineering results, generated bitstreams, P&R logs, example designs, and hardware-validation results.