| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| How to Map Verilog Design Exclusively to Custom Standard Cells in Yosys |
|
3 | 88 | August 19, 2025 |
| Support for Multiple SMT-LIB expressions |
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1 | 43 | July 31, 2025 |
| Support for package import (unexpected TOK_ID) |
|
3 | 76 | July 10, 2025 |
| Write_firrtl fails |
|
2 | 43 | June 24, 2025 |
| Filtering internal cell details in nexpnr timing reports |
|
2 | 53 | June 23, 2025 |
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|
1 | 72 | June 23, 2025 |
| Docker Images for oss-cad-suite/etc.? |
|
3 | 54 | June 11, 2025 |
| Disabling serdes on ECP5UM-5G FPGAs to save power |
|
0 | 67 | June 10, 2025 |
| SystemVerilog Assertions in Yosys |
|
1 | 138 | June 9, 2025 |
| General Queries on PLL usage with ECP5 |
|
2 | 128 | June 4, 2025 |