# \#circt

**URL:** https://yosyshq.discourse.group/tag/circt/1.md

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## [RFC: Announcing the new intermediate representation Property IR for assertions (SVA/PSL)](https://yosyshq.discourse.group/t/rfc-announcing-the-new-intermediate-representation-property-ir-for-assertions-sva-psl/143)

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**Author:** [@lena](https://yosyshq.discourse.group/u/lena)\
**Replies:** 4\
**Last updated:** [May 18, 2026, 4:13am UTC](https://yosyshq.discourse.group/t/rfc-announcing-the-new-intermediate-representation-property-ir-for-assertions-sva-psl/143 "2026-05-18T04:13:05Z")

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Property IR is a new intermediate representation for temporal properties as specified by SystemVerilog Assertions (SVA). The goal is to support formal verification flows, while decoupling front-end tasks (parsing, name r…

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## [Announcing the RTLIL MLIR dialect for CIRCT](https://yosyshq.discourse.group/t/announcing-the-rtlil-mlir-dialect-for-circt/75)

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**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\
**Replies:** 1\
**Last updated:** [September 22, 2025, 6:40am UTC](https://yosyshq.discourse.group/t/announcing-the-rtlil-mlir-dialect-for-circt/75 "2025-09-22T06:40:00Z")

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Under the OSVISE project, Yosys is growing a direct connection to the CIRCT project. CIRCT, notably used in the implementation of Chisel, extends MLIR for the purposes of hardware synthesis and formal verification. Curr…