# Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)

**URL:** https://yosyshq.discourse.group/t/yosys-0-61-21-up5k-48mhz-internal-clock-wont-build-no-pll/131
**Category:** Users
**Created:** [March 14, 2026, 12:13pm UTC](https://yosyshq.discourse.group/t/yosys-0-61-21-up5k-48mhz-internal-clock-wont-build-no-pll/131 "2026-03-14T12:13:14Z")
**Posts on this page:** 3
**Page:** 1

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### Author: ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)
#### Post date: [March 14, 2026, 12:13pm UTC](https://yosyshq.discourse.group/t/yosys-0-61-21-up5k-48mhz-internal-clock-wont-build-no-pll/131/1 "2026-03-14T12:13:14Z")

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Using either no definition or 0b00

output states :

ERROR: max frequency for clock is 46.6mhz (FAIL at 48:00 Mhz)

is this a bug? is there a workaround?

seems rather odd, this is very simple code.

```auto
SB_HFOSC u_hfosc (
	.CLKHFPU(1'b1),
	.CLKHFEN(1'b1),
	.CLKHF(int_osc)
);

```

filed as [#5751](https://github.com/YosysHQ/yosys/issues/5751)

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### Author: ![absurdfatalism](https://yyz2.discourse-cdn.com/free1/user_avatar/yosyshq.discourse.group/absurdfatalism/32/5_2.png) [@absurdfatalism](https://yosyshq.discourse.group/u/absurdfatalism)
#### Post date: [March 16, 2026, 2:18pm UTC](https://yosyshq.discourse.group/t/yosys-0-61-21-up5k-48mhz-internal-clock-wont-build-no-pll/131/2 "2026-03-16T14:18:53Z")

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Is your entire design just the HFOSC and you still fail timing? Typically that error is saying the logic part of your design failed to meet timing. What does the reported critical path look like? hmm

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<div class="post-metadata">

### Author: ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)
#### Post date: [March 16, 2026, 6:04pm UTC](https://yosyshq.discourse.group/t/yosys-0-61-21-up5k-48mhz-internal-clock-wont-build-no-pll/131/3 "2026-03-16T18:04:00Z")

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yup,

I’ve arrived from Radiant, and finding the reporting ‘different’.

I’ll get there.

xx