# SystemVerilog 2012 Parsing for RVFI
**URL:** https://yosyshq.discourse.group/t/systemverilog-2012-parsing-for-rvfi/73
**Category:** Users
**Created:** [August 23, 2025, 7:51am UTC](https://yosyshq.discourse.group/t/systemverilog-2012-parsing-for-rvfi/73 "2025-08-23T07:51:27Z")
**Posts on this page:** 2
**Page:** 1
### Author:  [@cherry-bunny779](https://yosyshq.discourse.group/u/cherry-bunny779)
#### Post date: [August 23, 2025, 7:51am UTC](https://yosyshq.discourse.group/t/systemverilog-2012-parsing-for-rvfi/73/1 "2025-08-23T07:51:27Z")
Hello, I am having a similar issue with an earlier post with the title “[Support for package import (unexpected TOK\_ID)](https://yosyshq.discourse.group/t/support-for-package-import-unexpected-tok-id/56)”. Except that I am attempting to run the RVFI verification flow on the **[cv32e40x](https://github.com/openhwgroup/cv32e40x)**
processor, and the rtl code has some features of System Verilog 2012, which I believe is causing the ‘unexpected TOK\_ID’.
It seems I need to attach a frontend that supports System Verilog 2012 in order to parse the files correctly, and I found out UHDM seems to serve that purpose. It’s not clear to me how to attach the frontend to RVFI.
I would greatly appreciate your help if you know of any related documentation I am missing, or if you see a better approach to this task. Thanks!
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### Author:  [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)
#### Post date: [August 31, 2025, 10:57pm UTC](https://yosyshq.discourse.group/t/systemverilog-2012-parsing-for-rvfi/73/2 "2025-08-31T22:57:32Z")
riscv-formal is quite tightly integrated with SBY (and Yosys by extension). There is a [blog post](https://blog.yosyshq.com/p/risc-v-formal-verification-framework-extension-for-synopsys-vc-formal/) about using riscv-formal with another tool (Synopsys) instead, and how the SBY files can be converted to achieve that. Or you could use something like [yosys-slang](https://github.com/povik/yosys-slang) to read the core, and use riscv-formal as normal.