# Support for package import (unexpected TOK\_ID)

**URL:** <https://yosyshq.discourse.group/t/support-for-package-import-unexpected-tok-id/56>\
**Category:** Users\
**Created:** [July 7, 2025, 4:35pm UTC](https://yosyshq.discourse.group/t/support-for-package-import-unexpected-tok-id/56 "2025-07-07T16:35:49Z")\
**Posts on this page:** 4\
**Page:** 1

<div class="post-metadata">

**Author:** ![manish](https://avatars.discourse-cdn.com/v4/letter/m/a6a055/32.png) [@manish](https://yosyshq.discourse.group/u/manish)\
**Post date:** [July 7, 2025, 4:35pm UTC](https://yosyshq.discourse.group/t/support-for-package-import-unexpected-tok-id/56/1 "2025-07-07T16:35:49Z")

</div>

Hello, I am trying to compile an SV module that imports packages defined separately.  
i.e cache\_ctl\_pkg.sv has

```auto
package cache_ctl_pkg;
  parameter MAIN_MEM_ADDRESS_WIDTH = 10;
  parameter BIT_DEPTH = 3; 
endpackage: cache_ctl_pkg

```

fifo\_rtl.sv has:

```auto
import cache_ctl_pkg::*;
typedef logic [MAIN_MEM_ADDRESS_WIDTH-1 : 0] word_t;
typedef word_t [0 : (2**BIT_DEPTH-1)] buffer_t;

```

When compiling with yosys(with TabbyCAD license), I get this  
`fifo_rtl.sv:1: ERROR: syntax error, unexpected TOK_ID`

I tried looking it up but could not find much if Yosys does/not support Wildcard import.

Any help in pointing out what I maybe doing wrong would be of great help. Thanks!

---

<div class="post-metadata">

**Author:** ![KrystalDelusion](https://avatars.discourse-cdn.com/v4/letter/k/8baadc/32.png) [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)\
**Post date:** [July 8, 2025, 7:51am UTC](https://yosyshq.discourse.group/t/support-for-package-import-unexpected-tok-id/56/2 "2025-07-08T07:51:58Z")

</div>

You mentioned TabbyCAD, but that looks like an error from read\_verilog. What is the script you’re using to load the design?

---

<div class="post-metadata">

**Author:** ![manish](https://avatars.discourse-cdn.com/v4/letter/m/a6a055/32.png) [@manish](https://yosyshq.discourse.group/u/manish)\
**Post date:** [July 9, 2025, 5:03pm UTC](https://yosyshq.discourse.group/t/support-for-package-import-unexpected-tok-id/56/3 "2025-07-09T17:03:05Z")

</div>

I have TabbyCAD License, but before running any verification with sby, I am just trying to compile in yosys with read\_verilog.

Here is how I am trying to compile it:  
I have just the two .sv files in a directory (fifo\_rtl.sv, cache\_ctl\_pkg.sv)

After loading yosys:

```auto
yosys> read_verilog -sv *.sv

1. Executing Verilog-2005 frontend: cache_ctl_pkg.sv
Parsing SystemVerilog input from `cache_ctl_pkg.sv' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: fifo_rtl.sv
Parsing SystemVerilog input from `fifo_rtl.sv' to AST representation.
fifo_rtl.sv:1: ERROR: syntax error, unexpected TOK_ID

```

I also tried compiling just the top file(fifo\_rtl.sv)

```auto
yosys> read_verilog -sv fifo_rtl.sv

1. Executing Verilog-2005 frontend: fifo_rtl.sv
Parsing SystemVerilog input from `fifo_rtl.sv' to AST representation.
fifo_rtl.sv:1: ERROR: syntax error, unexpected TOK_ID

```

Am I doing it correctly? Please let me know if I am missing something here. At the moment my interest is in compiling the design in Yosys, run simulation and then move to verification aspects later on. I am facing issues in compiling the design. This is the snippet where it fails.

Some info about my Yosys install:

```auto
⦗Tabby CAD Suite⦘ *** $ yosys

 /----------------------------------------------------------------------------\
 | yosys -- Yosys Open SYnthesis Suite -- YosysHQ Edition [202408060857] |
 | Copyright (C) 2012 - 2024 YosysHQ GmbH |
 | For support, please contact support@yosyshq.com |
 \----------------------------------------------------------------------------/
 Yosys 0.44 (git sha1 80ba43d26, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

```

Happy to provide any more information. Thank you!

---

<div class="post-metadata">

**Author:** ![KrystalDelusion](https://avatars.discourse-cdn.com/v4/letter/k/8baadc/32.png) [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)\
**Post date:** [July 10, 2025, 2:06am UTC](https://yosyshq.discourse.group/t/support-for-package-import-unexpected-tok-id/56/4 "2025-07-10T02:06:58Z")

</div>

You need to first read the file which declares the package, and then the file which uses the package; but I think the `read_verilog` frontend doesn’t support the `import` keyword and you would have to use `cache_ctl_pkg::MAIN_MEM_ADDRESS_WIDTH` etc to reference things in the package.

Alternatively, since you have the TabbyCAD Suite, you can use the Verific front end to load the SystemVerilog instead, which _does_ support `import`. You can do that with `read` instead of `read_verilog` (which will fall back to using `read_verilog` if `verific` is unavailable), or by explicitly calling `verific -sv cache_ctl_pkg.sv fifo_rtl.sv`.