# SRMODE = "CE\_OVER\_LSR" how to implement in Yosys?

**URL:** <https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123>\
**Category:** Users\
**Created:** [February 20, 2026, 12:54pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123 "2026-02-20T12:54:18Z")\
**Posts on this page:** 18\
**Page:** 1

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**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [February 20, 2026, 12:54pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/1 "2026-02-20T12:54:18Z")

</div>

FD1P3XZ my\_reg [7:0] {

.D(),

.SP(),

.CK(),

.SR(),

.Q(),

}

regarding SR type latches I found:

> **[Registers - YosysHQ Yosys 0.62-dev documentation](https://yosyshq.readthedocs.io/projects/yosys/en/latest/cell/word_reg.html)**

However, this did not provide immediate relief!!

The above snippet builds (UP5K) on Lattice Radiant, under Yosys reports:

Can’t find object for defparam my\_reg

I moved to Yosys some years ago, just happened to avoid needing to use this.

[Migrating Icecube2 to Radiant](https://www.google.com/url?sa=t&source=web&rct=j&opi=89978449&url=https://pages.hmc.edu/brake/class/e155/fa23/assets/doc/Radiant20_migration_icecube2.pdf&ved=2ahUKEwjn4fTwnuiSAxVxU0EAHe29DcsQFnoECB8QAQ&usg=AOvVaw3EaM_p9_xQMIpDgVDTS2m8) references: FD1P3XZ primitive instantiation

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**Author:** ![widlarizer](https://avatars.discourse-cdn.com/v4/letter/w/bbce88/32.png) [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\
**Post date:** [February 20, 2026, 3:19pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/2 "2026-02-20T15:19:29Z")

</div>

You’ve got a couple of options and you aren’t being very specific.

### Inference

The doc you link says that you can either “let the synthesis infer register functions from the source RTL”. That should work well for synchronous flops, and unfortunately not as well yet for asynchronous. I have some code for improving asynchronous flip flop inference that hasn’t been integrated yet.

Track asynchronous flip flop improvements here:

- [$dffsr semantics as implemented differ from models and docs · Issue #5194 · YosysHQ/yosys · GitHub](https://github.com/YosysHQ/yosys/issues/5194)
- [Make async flip flops easy to opt with new $priority cell by widlarizer · Pull Request #5613 · YosysHQ/yosys · GitHub](https://github.com/YosysHQ/yosys/pull/5613)
- [Undefine set&reset behavior of $dffsr by widlarizer · Pull Request #5655 · YosysHQ/yosys · GitHub](https://github.com/YosysHQ/yosys/pull/5655)

### Instantiating Yosys-internal cells

The docs page you’re linking is about the “word-level” register cells. For single-bit but technology-unspecific cells, there’s this page:

> **[Flip-flop cells - YosysHQ Yosys 0.62-dev documentation](https://yosyshq.readthedocs.io/projects/yosys/en/latest/cell/gate_reg_ff.html)**

> The cell types `$_SDFFCE_[NP][NP][01][NP]_` implement d-type flip-flops with synchronous reset and enable, with enable having priority over reset

From there you could either directly instantiate the Yosys-internal `$_SDFFCE_...` type that corresponds to the polarities you want.

### Instantiating iCEcube2 style cells

You can see in [this file](https://github.com/YosysHQ/yosys/blob/main/techlibs/ice40/ff_map.v) that those kinds of cells map to ice40-specific cells `SB_DFFE...` and `SB_DFFNE...`. Their behavioral models are [here](https://github.com/YosysHQ/yosys/blob/main/techlibs/ice40/cells_sim.v). These are apparently iCEcube2 names for these primitives. Yosys “knows” these ice40-specific cell types, so you might want to use those instead.

### Instantiating Radiant style cells

Yosys can’t resolve FD1P3XZ with parameters, it doesn’t know what that is. The doc you link even suggests you should instead instantiate FD1P3IZ or whatever, which doesn’t need parameters. Instantiating that and adding an empty FD1P3IZ module (this causes it to be interpreted as a “blackbox”) should work too.

I think we could turn this reply of mine into an application note at this point…

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**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [February 20, 2026, 3:53pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/3 "2026-02-20T15:53:09Z")

</div>

Hi [widlarizer](https://yosyshq.discourse.group/u/widlarizer), many thanks for the prompt and lengthy response.

I’ve attached the complete module, it comes from a project provided by Lattice, and I have no idea how to follow your guide, and would be grateful, if further instruction was available.

Whether this module could contribute to the application note I cannot say.

Thank you once again!

module ice40\_resetn(  
input clk,  
output resetn  
);

wire [7:0] cnt;  
wire [7:0] cnt\_in;  
wire cnt\_en;  
wire r\_resetn;

FD1P3XZ u\_cnt\_reg [7:0] (  
.D(cnt\_in),  
.SP(cnt\_en),  
.CK(clk),  
.SR(1’b0),  
.Q(cnt));  
defparam u\_cnt\_reg[7].REGSET = “RESET”;  
defparam u\_cnt\_reg[6].REGSET = “RESET”;  
defparam u\_cnt\_reg[5].REGSET = “RESET”;  
defparam u\_cnt\_reg[4].REGSET = “RESET”;  
defparam u\_cnt\_reg[3].REGSET = “RESET”;  
defparam u\_cnt\_reg[2].REGSET = “RESET”;  
defparam u\_cnt\_reg[1].REGSET = “RESET”;  
defparam u\_cnt\_reg[0].REGSET = “RESET”;  
defparam u\_cnt\_reg[7].SRMODE = “CE\_OVER\_LSR”;  
defparam u\_cnt\_reg[6].SRMODE = “CE\_OVER\_LSR”;  
defparam u\_cnt\_reg[5].SRMODE = “CE\_OVER\_LSR”;  
defparam u\_cnt\_reg[4].SRMODE = “CE\_OVER\_LSR”;  
defparam u\_cnt\_reg[3].SRMODE = “CE\_OVER\_LSR”;  
defparam u\_cnt\_reg[2].SRMODE = “CE\_OVER\_LSR”;  
defparam u\_cnt\_reg[1].SRMODE = “CE\_OVER\_LSR”;  
defparam u\_cnt\_reg[0].SRMODE = “CE\_OVER\_LSR”;

FD1P3XZ u\_r\_resetn0 (  
.D(1’b1 ),  
.SP(!cnt\_en),  
.CK(clk),  
.SR(1’b0),  
.Q(r\_resetn));  
defparam u\_r\_resetn0.REGSET = “RESET”;  
defparam u\_r\_resetn0.SRMODE = “CE\_OVER\_LSR”;

assign resetn = r\_resetn;  
assign cnt\_in = cnt + 8’d1;  
assign cnt\_en = (cnt != 8’hff);

endmodule

---

<div class="post-metadata">

**Author:** ![widlarizer](https://avatars.discourse-cdn.com/v4/letter/w/bbce88/32.png) [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\
**Post date:** [February 20, 2026, 4:03pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/4 "2026-02-20T16:03:28Z")

</div>

It’s up to you to know what sort of flip flop you want, not up to me to guess. If it’s not your Verilog, but from Lattice, ask Lattice. Looking up “FD1P3XZ” including the quotes on Google finds nothing that would define what it’s supposed to do with what sort of parameter

There’s no point in feeding code nobody understands into Yosys or any other tool

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**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [February 20, 2026, 4:32pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/5 "2026-02-20T16:32:55Z")

</div>

Many thanks, chasing…

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**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [February 26, 2026, 3:36pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/6 "2026-02-26T15:36:42Z")

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I wrote to the author asking about FD1P3XZ he replied to me: “You can use any old flop for this…”

tx

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**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [February 27, 2026, 5:45pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/7 "2026-02-27T17:45:03Z")

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Hi widlarizer,

regarding: Instantiating that and adding an empty FD1P3IZ module (this causes it to be interpreted as a “blackbox”) should work too.

FD1P3DZ wfm in Radiant without parameters.

When building with Yosys, I added an empty module named FD1P3DZ,

however error FD1P3DZ does not have a port named ‘Q’ is output.

else if the ports are included FD1P3DZ is not supported.

what did I not understand?

I did not find any example of any use in verilog in the wild, including github

Thank you again

---

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**Author:** ![KrystalDelusion](https://avatars.discourse-cdn.com/v4/letter/k/8baadc/32.png) [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)\
**Post date:** [February 27, 2026, 8:27pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/8 "2026-02-27T20:27:27Z")

</div>

When adding an empty module it should still have the correct ports, just not have any implementation (anything after the port definition). e.g.

```verilog
module FD1S3IX(input CD, D, CK, output Q);
endmodule

```

---

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**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [February 27, 2026, 8:50pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/9 "2026-02-27T20:50:52Z")

</div>

Hi KrystalDelusion,

thanks, I’m using

module FD1P3DZ(input D, CK, SP, CD, output Q);  
endmodule

whilst FD1P3DZ builds under Radiant, under Yosys response is “unsupported”

I did not find .sp as port, but something similar (enable port) is needed, I tried E without luck

---

<div class="post-metadata">

**Author:** ![KrystalDelusion](https://avatars.discourse-cdn.com/v4/letter/k/8baadc/32.png) [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)\
**Post date:** [February 27, 2026, 8:51pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/10 "2026-02-27T20:51:48Z")

</div>

Can you provide a minimal reproducer showing your problem?

---

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**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [February 27, 2026, 10:10pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/11 "2026-02-27T22:10:34Z")

</div>

This module builds and does the necessary under Radiant:

module ice40\_resetn(  
input clk,  
output resetn  
);

wire [7:0] cnt;  
wire [7:0] cnt\_in;  
wire cnt\_en;  
wire r\_resetn;

FD1P3DZ u\_cnt\_reg [7:0](  
.D (cnt\_in),//I: data in  
.CK (clk), //I: clock input  
.SP (cnt\_en),//ce);  
.CD (1’b0),//I: sync reset input  
.Q (cnt)//O: data out  
);

FD1P3DZ u\_r\_resetn0 (  
.D (1’b1), //I: data in  
.CK (clk), //I: clock input  
.SP (!cnt\_en),//ce);  
.CD (1’b0),//I: sync reset input  
.Q (r\_resetn)//O: data out  
);

assign resetn = r\_resetn;  
assign cnt\_in = cnt + 8’d1;  
assign cnt\_en = (cnt != 8’hff);

endmodule

I have tried adding various blank modules, but none build under Yosys, so far

---

<div class="post-metadata">

**Author:** ![KrystalDelusion](https://avatars.discourse-cdn.com/v4/letter/k/8baadc/32.png) [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)\
**Post date:** [February 27, 2026, 10:18pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/12 "2026-02-27T22:18:58Z")

</div>

```auto
read_verilog << EOT
module FD1P3DZ (input D, CK, SP, CD, output Q);
endmodule

module ice40_resetn(
input clk,
output resetn
);

wire [7:0] cnt;
wire [7:0] cnt_in;
wire cnt_en;
wire r_resetn;

FD1P3DZ u_cnt_reg [7:0](
.D (cnt_in),//I: data in
.CK (clk), //I: clock input
.SP (cnt_en),//ce);
.CD (1'b0),//I: sync reset input
.Q (cnt)//O: data out
);

FD1P3DZ u_r_resetn0 (
.D (1'b1), //I: data in
.CK (clk), //I: clock input
.SP (!cnt_en),//ce);
.CD (1'b0),//I: sync reset input
.Q (r_resetn)//O: data out
);

assign resetn = r_resetn;
assign cnt_in = cnt + 8'd1;
assign cnt_en = (cnt != 8'hff);

endmodule
EOT

synth_ice40 -device u -top ice40_resetn

```

works fine with Yosys 0.61

---

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**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [February 28, 2026, 8:25am UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/13 "2026-02-28T08:25:15Z")

</div>

Thank you so much, however on my system Yosys 0.61+21 output is

ERROR: cell type ‘FD1P3DZ’ is unsupported (instantiated as ‘VII.u\_resetn.u\_cnt\_reg[5]’)

0 warnings 1 error

make: \*\*\* [Makefile:12: top.asc] error 255

Copied and pasted to avoid typos.

yosys -p 'synth\_ice40 -json top.json’

How to proceed? UP5K SG48

---

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**Author:** ![KrystalDelusion](https://avatars.discourse-cdn.com/v4/letter/k/8baadc/32.png) [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)\
**Post date:** [February 28, 2026, 10:50pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/14 "2026-02-28T22:50:45Z")

</div>

Does the code I included work for you?

---

<div class="post-metadata">

**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [March 1, 2026, 12:34pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/15 "2026-03-01T12:34:05Z")

</div>

It does not, but I switched to using always@.

---

<div class="post-metadata">

**Author:** ![KrystalDelusion](https://avatars.discourse-cdn.com/v4/letter/k/8baadc/32.png) [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)\
**Post date:** [March 1, 2026, 7:10pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/16 "2026-03-01T19:10:50Z")

</div>

Can you post a log file with the error?

---

<div class="post-metadata">

**Author:** ![widlarizer](https://avatars.discourse-cdn.com/v4/letter/w/bbce88/32.png) [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\
**Post date:** [March 5, 2026, 3:41pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/17 "2026-03-05T15:41:14Z")

</div>

That’s a nextpnr error, not yosys. You only asked about yosys. You can use iCEcube2 style cells instead as I suggested, I checked and nextpnr seems to understand only SB\_DFF\* style cells for ice40. FD1P3BX, FD1P3DX, FD1P3IX, FD1P3JX are supported for the nexus familiy

---

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**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [March 5, 2026, 5:29pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123/18 "2026-03-05T17:29:19Z")

</div>

Emil,

that’s really kind, in a bit deep for me, but good for the search trail

thank you

xx