# Issue with Defining Power Pins in Standalone Yosys (USE\_POWER\_PINS not taking effect)

**URL:** <https://yosyshq.discourse.group/t/issue-with-defining-power-pins-in-standalone-yosys-use-power-pins-not-taking-effect/144>\
**Category:** Users\
**Created:** [May 12, 2026, 12:23pm UTC](https://yosyshq.discourse.group/t/issue-with-defining-power-pins-in-standalone-yosys-use-power-pins-not-taking-effect/144 "2026-05-12T12:23:19Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Vishal](https://avatars.discourse-cdn.com/v4/letter/v/49beb7/32.png) [@Vishal](https://yosyshq.discourse.group/u/Vishal)\
**Post date:** [May 12, 2026, 12:23pm UTC](https://yosyshq.discourse.group/t/issue-with-defining-power-pins-in-standalone-yosys-use-power-pins-not-taking-effect/144/1 "2026-05-12T12:23:19Z")

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Hi  
I am using Standalone Yosys Version 0.62 for RTL synthesis. In my design, some modules include power pins conditionally using the following Verilog construct:

`ifdef USE_POWER_PINS`  
` .VPWR(vccd),`  
` .VGND(vssd),`  
` `endif

To enable this, I have added the following in my Yosys script (\*.ys file):  
verilog\_defines -D USE\_POWER\_PINS

However, the macro does not seem to be taking effect during synthesis, and the power pins are not being included in the design as expected.

Could you please clarify:

- The correct way to define `USE_POWER_PINS` in standalone Yosys 0.62

- Whether `verilog_defines` is sufficient or if another method is required

- If there is support for something like `NTH_USE_PG_PINS_DEFINES` or similar in the Yosys script

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**Author:** ![KrystalDelusion](https://avatars.discourse-cdn.com/v4/letter/k/8baadc/32.png) [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)\
**Post date:** [May 15, 2026, 5:19am UTC](https://yosyshq.discourse.group/t/issue-with-defining-power-pins-in-standalone-yosys-use-power-pins-not-taking-effect/144/2 "2026-05-15T05:19:17Z")

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What frontend are you using to parse your input? `verilog_defines` only works with `read_verilog`. You can also usually provide the `-D<name>` during the read call, e.g. `read_verilog -DUSE_POWER_PINS <input.v>`. Also make sure that you are calling `verilog_defines` prior to the relevant `read_verilog`. I’m not sure what you mean by `NTH_USE_PG_PINS_DEFINES`?