# Is This a Forum where I Can Ask Questions about Verilog?

**URL:** <https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156>\
**Category:** Users\
**Created:** [August 14, 2026, 12:19am UTC](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156 "2026-08-14T00:19:46Z")\
**Posts on this page:** 6\
**Page:** 1

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**Author:** ![kvnsmnsn](https://avatars.discourse-cdn.com/v4/letter/k/f08c70/32.png) [@kvnsmnsn](https://yosyshq.discourse.group/u/kvnsmnsn)\
**Post date:** [August 14, 2026, 12:19am UTC](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156/1 "2026-08-14T00:19:46Z")

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I’ve got a bit of Verilog code, and I’m wondering what it actually does, how it actually gets implemented. Is this a good forum to discuss that? If not, can someone point me to a forum that is more appropriate?

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**Author:** ![kvnsmnsn](https://avatars.discourse-cdn.com/v4/letter/k/f08c70/32.png) [@kvnsmnsn](https://yosyshq.discourse.group/u/kvnsmnsn)\
**Post date:** [August 14, 2026, 10:20pm UTC](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156/2 "2026-08-14T22:20:59Z")

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It’s been almost 24 hours since I made my initial post, so in case the answer to my first question is yes, I thought I’d write my Verilog code. It is:

```verilog
module LessThan #( nmBits = 1)
( output rslt
, input [nmBits-1:0] lftOp
, input [nmBits-1:0] rhtOp);
assign rslt = lftOp < rhtOp;
endmodule

```

Now obviously output (rslt) is going to be a logical one if the integer represented by (lftOp) is mathematically less than the integer represented by (rhtOp), and (rslt) is going to be a logical zero otherwise. But the textbook for my VLSI Design class I took Fall 2024 at Utah Valley University says that the way this is usually calculated is to subtract (rhtOp) from (lftOp) and see if there’s a carry. If I just have this Verilog code and instantiate the (LessThan) module, will my circuit do that subtract, or will it calculate it some other way? I ask this because I think I have an algorithm that will calculate the right value without doing the subtract, and I’m curious whether or not my algorithm might be more efficient and less expensive.

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**Author:** ![KrystalDelusion](https://avatars.discourse-cdn.com/v4/letter/k/8baadc/32.png) [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)\
**Post date:** [August 16, 2026, 9:52pm UTC](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156/3 "2026-08-16T21:52:10Z")

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Efficiency is a pretty nebulous metric at the best of times, and what is considered expensive is going to vary depending on the platform used and resources available. Given that this is the Yosys discussion forum, I can tell you that loading the code with `yosys` (and calling `hierarchy; opt; alumacc;`) does indeed use a subtraction and uses the carry out to determine the comparison result:

 ![image](https://global.discourse-cdn.com/free1/uploads/yosyshq/original/1X/1a3f7cb72d1b354a0eb1b0b05e60c65fe19b9787.png)

If you can map the `$alu` directly to a single cell (say a hardware DSP) then this is probably quite efficient. If you’re building out full adders then maybe less so:

 ![image](https://global.discourse-cdn.com/free1/uploads/yosyshq/original/1X/2fb725f0092e16988c5a2660d47d2a68290743e2.png)

(that’s after a call to `techmap` and `opt` for `nmBits=1`). If you’re just wanting to look at gate counts for simple cells you can just do that (and even prove that the outputs are equivalent with `equiv`). But I suspect if you’re mapping to actual hardware it gets more complicated when you start taking into account things like propagation delay and routing congestion.

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**Author:** ![kvnsmnsn](https://avatars.discourse-cdn.com/v4/letter/k/f08c70/32.png) [@kvnsmnsn](https://yosyshq.discourse.group/u/kvnsmnsn)\
**Post date:** [August 19, 2026, 4:14pm UTC](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156/4 "2026-08-19T16:14:17Z")

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KrystalDelusion: “If you can map the ($alu) directly to a single cell (say a hardware DSP) then this is probably quite efficient. If you’re building out full adders then maybe less so:” This sounds like you’re saying there already is an algorithm for calculating (LessThan) that doesn’t involve full adders. In fact, your first diagram appears to be an illustration of such a circuit. However, I’m at a loss as to what that diagram actually means. Can you elaborate on it? You’ve got a box on the left with ($7/$alu) in the middle, (A/B/Bl/Cl) on the left, and (CO/X/Y) on the right. What exactly do all of them mean? Keep in mind that my whole career amounts to five years of audited Computer Engineering classes at Utah Valley University.

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**Author:** ![KrystalDelusion](https://avatars.discourse-cdn.com/v4/letter/k/8baadc/32.png) [@KrystalDelusion](https://yosyshq.discourse.group/u/KrystalDelusion)\
**Post date:** [August 19, 2026, 10:01pm UTC](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156/5 "2026-08-19T22:01:53Z")

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The images above are generated with the `show` command in Yosys, which you can see [documentation for](https://yosyshq.readthedocs.io/projects/yosys/en/latest/getting_started/scripting_intro.html#displaying-schematics). But in short, the boxes are cells (module instances), the top line (`$7`) is the name of the cell, the bottom line (`$alu`) is the name of the module being instantiated (also referred to as the “type”). Module names beginning with `$` are built-in types, cell (or wire) names beginning with `$` are auto generated (also referred to as “private”, in contrast with user-provided names which are “public”).

The `$alu` here is doing a subtraction, `CI=1, BI=1` are the carry-in and invert-b signals (both of which are set for a subtraction), `X` is the result of `A - B`, `CO` is the carry-out, and `Y` is `A xor B` (which gets used for equality comparisons, such as if you’re doing `>=`). You can also take a look at the [arithmetic logic unit documentation](https://yosyshq.readthedocs.io/projects/yosys/en/latest/cell/word_arith.html#arith.$alu).

If you call `show` after `hierarchy` you’ll see that the circuit generated contains a `$lt` cell, `alumacc` then converts the `$lt` to a subtraction operation carried out by an `$alu`.

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**Author:** ![peepo](https://avatars.discourse-cdn.com/v4/letter/p/839c29/32.png) [@peepo](https://yosyshq.discourse.group/u/peepo)\
**Post date:** [September 1, 2026, 8:34am UTC](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156/6 "2026-09-01T08:34:23Z")

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The answer can depend on the number of bits in the integer, which you do not specify.

see: [https://www.electronics-tutorials.ws/combination/comb\_8.html](https://www.electronics-tutorials.ws/combination/comb_8.html)

x:"