# How do you lint your Yosys Verilog projects?

**URL:** <https://yosyshq.discourse.group/t/how-do-you-lint-your-yosys-verilog-projects/117>\
**Category:** Users\
**Created:** [January 25, 2026, 3:06am UTC](https://yosyshq.discourse.group/t/how-do-you-lint-your-yosys-verilog-projects/117 "2026-01-25T03:06:26Z")\
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**Author:** ![zapta](https://avatars.discourse-cdn.com/v4/letter/z/97f17d/32.png) [@zapta](https://yosyshq.discourse.group/u/zapta)\
**Post date:** [January 26, 2026, 5:36pm UTC](https://yosyshq.discourse.group/t/how-do-you-lint-your-yosys-verilog-projects/117/3 "2026-01-26T17:36:40Z")

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Does icarus verilog work better in linting Yosys projects and libraries?

I tried verilator and verible-verilog-lint and they fail.

Regardless of the tool, I think that Yosys should have at least one known good linter that is also be used in Yosys automated testing.

> [@\[Proposal\] Automatic test for Yosys cell libraries?](https://yosyshq.discourse.group/t/proposal-automatic-test-for-yosys-cell-libraries/118):
>
> Background: Yosys recommends linting projects with Verilator and the oss-cad-suite package includes a Verilator binary. [https://github.com/YosysHQ/yosys/blob/main/README.md#additional-information](https://github.com/YosysHQ/yosys/blob/main/README.md#additional-information) Yosys standard libraries throw tons of warnings with linting a project, requiring the user to create Verilator rule suppression file. This PR [synth\_ecp5 and synth\_nexus to synth\_lattice by mmicko · Pull Request #3908 · YosysHQ/yosys · GitHub](https://github.com/YosysHQ/yosys/pull/3908) from October 2025 broke the ECP5 linting completely with a f…

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