# Latest **URL:** https://yosyshq.discourse.group/latest.md [Latest](https://yosyshq.discourse.group/latest.md) · [Categories](https://yosyshq.discourse.group/categories.md) · [Tags](https://yosyshq.discourse.group/tags.md) --- ## [Adding a pass for Multiple Constant Multiplication (mcm)](https://yosyshq.discourse.group/t/adding-a-pass-for-multiple-constant-multiplication-mcm/165)
**Author:** [@hfthra](https://yosyshq.discourse.group/u/hfthra)\ **Replies:** 6\ **Last updated:** [September 21, 2026, 12:31pm UTC](https://yosyshq.discourse.group/t/adding-a-pass-for-multiple-constant-multiplication-mcm/165 "2026-09-21T12:31:10Z")
I am creating a new pass for restructuring multiplication with constants into shifts with addition/subtraction. $mul operations with constants will be implemented as shifts, which results in a smaller mapped area than im… --- ## [Reverse-engineering Renesas ForgeFPGA SLG47910V for open-source Yosys/FPGA support](https://yosyshq.discourse.group/t/reverse-engineering-renesas-forgefpga-slg47910v-for-open-source-yosys-fpga-support/168)
**Author:** [@Aasssink786](https://yosyshq.discourse.group/u/Aasssink786)\ **Replies:** 0\ **Last updated:** [September 11, 2026, 8:47pm UTC](https://yosyshq.discourse.group/t/reverse-engineering-renesas-forgefpga-slg47910v-for-open-source-yosys-fpga-support/168 "2026-09-11T20:47:04Z")
Hi YosysHQ team, I’m currently working on reverse-engineering the Renesas ForgeFPGA SLG47910V architecture, used by the Vicharak Shrike family, with the goal of enabling a more open-source FPGA toolchain. I’m starting … --- ## [Is This a Forum where I Can Ask Questions about Verilog?](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156)
**Author:** [@kvnsmnsn](https://yosyshq.discourse.group/u/kvnsmnsn)\ **Replies:** 5\ **Last updated:** [September 1, 2026, 8:34am UTC](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156 "2026-09-01T08:34:23Z")
I’ve got a bit of Verilog code, and I’m wondering what it actually does, how it actually gets implemented. Is this a good forum to discuss that? If not, can someone point me to a forum that is more appropriate? --- ## [Interim LLM Policy](https://yosyshq.discourse.group/t/interim-llm-policy/163)
**Author:** [@Kate\_Yosys](https://yosyshq.discourse.group/u/Kate_Yosys)\ **Replies:** 0\ **Last updated:** [August 31, 2026, 1:49pm UTC](https://yosyshq.discourse.group/t/interim-llm-policy/163 "2026-08-31T13:49:10Z")
As the maintainers of OSS CAD suite and Tabby CAD suite, we’ve seen an increasing number of pull requests containing LLM generated code. Developing a consistent and unanimously accepted approach on how we intend to handl… --- ## [Sanity check: interpreting synth\_xilinx BRAM/LUT/FF counts in a memory-topology comparison](https://yosyshq.discourse.group/t/sanity-check-interpreting-synth-xilinx-bram-lut-ff-counts-in-a-memory-topology-comparison/159)
**Author:** [@AlexSafonov](https://yosyshq.discourse.group/u/AlexSafonov)\ **Replies:** 2\ **Last updated:** [August 28, 2026, 1:04pm UTC](https://yosyshq.discourse.group/t/sanity-check-interpreting-synth-xilinx-bram-lut-ff-counts-in-a-memory-topology-comparison/159 "2026-08-28T13:04:14Z")
Title: Sanity check: interpreting synth\_xilinx BRAM/LUT/FF counts in a memory-topology comparison Hi, I’m looking for a narrow Yosys methodology sanity check on PB-HW-04, a small structural comparison of four organizat… --- ## [An open-source high-level synthesis tool that accepts idiomatic Python](https://yosyshq.discourse.group/t/an-open-source-high-level-synthesis-tool-that-accepts-idiomatic-python/154)
**Author:** [@Pavel](https://yosyshq.discourse.group/u/Pavel)\ **Replies:** 4\ **Last updated:** [August 20, 2026, 9:37pm UTC](https://yosyshq.discourse.group/t/an-open-source-high-level-synthesis-tool-that-accepts-idiomatic-python/154 "2026-08-20T21:37:05Z")
Recently I’ve been working on a certain embedded system that has an FPGA running EKF and some controls. Coding that in RTL is inefficient at best so I turned to HLS and looked around to see what the industry has to offer… --- ## [Your CMake workflows](https://yosyshq.discourse.group/t/your-cmake-workflows/155)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 1\ **Last updated:** [July 23, 2026, 9:22pm UTC](https://yosyshq.discourse.group/t/your-cmake-workflows/155 "2026-07-23T21:22:30Z")
Since we switched Yosys to CMake, I wanted as simple a workflow as before. Thankfully user presets are super convenient. Here’s my presets file: With this I can do, for example, cmake --workflow --preset d to configure… --- ## [Equiv\_opt on hierarchical designs](https://yosyshq.discourse.group/t/equiv-opt-on-hierarchical-designs/152)
**Author:** [@donn](https://yosyshq.discourse.group/u/donn)\ **Replies:** 1\ **Last updated:** [June 22, 2026, 10:32pm UTC](https://yosyshq.discourse.group/t/equiv-opt-on-hierarchical-designs/152 "2026-06-22T22:32:20Z")
One of the tests I’m debugging currently runs a pass on a design that happens to have a submodule: read\_verilog \<\ **Author:** [@iztok.jeras](https://yosyshq.discourse.group/u/iztok.jeras)\ **Replies:** 1\ **Last updated:** [June 22, 2026, 4:30pm UTC](https://yosyshq.discourse.group/t/adding-support-for-latch-mapping-to-dfflibmap/153 "2026-06-22T16:30:38Z") I created a \[pull request\]( Update to \`dfflibmap\` to be able to map LATCHes by jeras · Pull Request #5976 · YosysHQ/yosys · GitHub ) draft which adds support for mapping LATCHes from a SCL Liberty file. The code is build… --- ## [Consistent source location transfer with Patch](https://yosyshq.discourse.group/t/consistent-source-location-transfer-with-patch/121)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 3\ **Last updated:** [June 11, 2026, 10:57am UTC](https://yosyshq.discourse.group/t/consistent-source-location-transfer-with-patch/121 "2026-06-11T10:57:57Z")
The greatest source of loss of source attributes is synthesis with abc, but not all users use abc and there’s a lot of gaps in Yosys passes. To address this, there’s two major features I think we need. Patch I have star… --- ## [Fixing \`IdString\` refcounting](https://yosyshq.discourse.group/t/fixing-idstring-refcounting/94)
**Author:** [@rocallahan](https://yosyshq.discourse.group/u/rocallahan)\ **Replies:** 11\ **Last updated:** [June 11, 2026, 6:36am UTC](https://yosyshq.discourse.group/t/fixing-idstring-refcounting/94 "2026-06-11T06:36:12Z")
IdString refcounting adds overhead and code bloat, and would be even more overhead if we try to make it make safe for multithreading, so it would be good to remove most or all of it. Instead of refcounting, we could try… --- ## [An update on C++-ification of logging APIs](https://yosyshq.discourse.group/t/an-update-on-c-ification-of-logging-apis/77)
**Author:** [@rocallahan](https://yosyshq.discourse.group/u/rocallahan)\ **Replies:** 5\ **Last updated:** [June 9, 2026, 5:56pm UTC](https://yosyshq.discourse.group/t/an-update-on-c-ification-of-logging-apis/77 "2026-06-09T17:56:49Z")
Until recently the Yosys stringf() and logging APIs used C-style variadic functions. That means C++ objects like std::string and std::string\_view can’t be passed directly, so the code is littered with .c\_str() calls… and… --- ## [Poll: LLMs - quality, morality, opportunity, policy](https://yosyshq.discourse.group/t/poll-llms-quality-morality-opportunity-policy/151)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 2\ **Last updated:** [May 29, 2026, 6:21pm UTC](https://yosyshq.discourse.group/t/poll-llms-quality-morality-opportunity-policy/151 "2026-05-29T18:21:04Z")
LLM contributions to Yosys are on the rise and we are considering adding LLM-specific rules to contribution guidelines. We’ve had brief discussions of the applicability of LLM coding tools internally, and I would like to… --- ## [Proving the prover, or "How do we verify we're constructing SVA assertions correctly?"](https://yosyshq.discourse.group/t/proving-the-prover-or-how-do-we-verify-were-constructing-sva-assertions-correctly/148)
**Author:** [@melyoung](https://yosyshq.discourse.group/u/melyoung)\ **Replies:** 3\ **Last updated:** [May 29, 2026, 4:01pm UTC](https://yosyshq.discourse.group/t/proving-the-prover-or-how-do-we-verify-were-constructing-sva-assertions-correctly/148 "2026-05-29T16:01:58Z")
Heya everyone, I’m working with povik and some other contributors (namely mndstrmr) to yosys-slang to add better support for SVA assertions over there (Rebase SVA support into main by mlyoung101 · Pull Request #317 · po… --- ## [Why is synth\_ecp5 flag \`-dff\` not enabled by default?](https://yosyshq.discourse.group/t/why-is-synth-ecp5-flag-dff-not-enabled-by-default/150)
**Author:** [@tambewilliam](https://yosyshq.discourse.group/u/tambewilliam)\ **Replies:** 1\ **Last updated:** [May 20, 2026, 1:50pm UTC](https://yosyshq.discourse.group/t/why-is-synth-ecp5-flag-dff-not-enabled-by-default/150 "2026-05-20T13:50:31Z")
My design appears to much easily meet timing when I use the synth\_ecp5 flag -dff, which run abc9 with -dff option. Is there a reason why it is not enabled by default ? Does it have drawbacks ? --- ## [RFC: Announcing the new intermediate representation Property IR for assertions (SVA/PSL)](https://yosyshq.discourse.group/t/rfc-announcing-the-new-intermediate-representation-property-ir-for-assertions-sva-psl/143)
**Author:** [@lena](https://yosyshq.discourse.group/u/lena)\ **Replies:** 4\ **Last updated:** [May 18, 2026, 4:13am UTC](https://yosyshq.discourse.group/t/rfc-announcing-the-new-intermediate-representation-property-ir-for-assertions-sva-psl/143 "2026-05-18T04:13:05Z")
Property IR is a new intermediate representation for temporal properties as specified by SystemVerilog Assertions (SVA). The goal is to support formal verification flows, while decoupling front-end tasks (parsing, name r… --- ## [Itp engine: fixpoint convergence and skip parameter](https://yosyshq.discourse.group/t/itp-engine-fixpoint-convergence-and-skip-parameter/149)
**Author:** [@inquisitour](https://yosyshq.discourse.group/u/inquisitour)\ **Replies:** 0\ **Last updated:** [May 15, 2026, 10:17pm UTC](https://yosyshq.discourse.group/t/itp-engine-fixpoint-convergence-and-skip-parameter/149 "2026-05-15T22:17:11Z")
Hello everyone, During benchmarking on riscv-formal cores (NERV, PicoRV32, SERV, VexRiscv) with the itp engine, I found fixpoint convergence works correctly with skip=0 but returns bounded results only when skip\>0. The … --- ## [Issue with Defining Power Pins in Standalone Yosys (USE\_POWER\_PINS not taking effect)](https://yosyshq.discourse.group/t/issue-with-defining-power-pins-in-standalone-yosys-use-power-pins-not-taking-effect/144)
**Author:** [@Vishal](https://yosyshq.discourse.group/u/Vishal)\ **Replies:** 1\ **Last updated:** [May 15, 2026, 5:19am UTC](https://yosyshq.discourse.group/t/issue-with-defining-power-pins-in-standalone-yosys-use-power-pins-not-taking-effect/144 "2026-05-15T05:19:17Z")
Hi I am using Standalone Yosys Version 0.62 for RTL synthesis. In my design, some modules include power pins conditionally using the following Verilog construct: ifdef USE\_POWER\_PINS .VPWR(vccd), .VGND(vssd… --- ## [timing closure degraded](https://yosyshq.discourse.group/t/timing-closure-degraded/139)
**Author:** [@tambewilliam](https://yosyshq.discourse.group/u/tambewilliam)\ **Replies:** 8\ **Last updated:** [May 13, 2026, 3:45pm UTC](https://yosyshq.discourse.group/t/timing-closure-degraded/139 "2026-05-13T15:45:46Z")
Between oss-cad-suite 20251204 (with nextpnr-0.9-43) and 20260415 (nextpnr-0.10-33), something changed such that nextpnr-ecp5, for the same exact design that used to pass 48 MHz timing, now fails achieving only 30 MHz. … --- ## [SDC support roadmap](https://yosyshq.discourse.group/t/sdc-support-roadmap/95)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 4\ **Last updated:** [May 7, 2026, 2:39pm UTC](https://yosyshq.discourse.group/t/sdc-support-roadmap/95 "2026-05-07T14:39:51Z")
There are several good reasons for Yosys to support various use cases that involve SDC. These use cases can be implemented in various ways. Here are my notes on the topic with some updates on how we’re going about to kic… --- ## [New PR with up to 2.57x performance improvements](https://yosyshq.discourse.group/t/new-pr-with-up-to-2-57x-performance-improvements/142)
**Author:** [@crockpotveggies](https://yosyshq.discourse.group/u/crockpotveggies)\ **Replies:** 3\ **Last updated:** [April 27, 2026, 8:33pm UTC](https://yosyshq.discourse.group/t/new-pr-with-up-to-2-57x-performance-improvements/142 "2026-04-27T20:33:16Z")
(numbers based on benchmarks and YMMV) I’ve opened a PR with some perf enhancements which I think will make a significant difference in speeding up some aspects of synthesis. I’ve sync’d with main and all tests appear t… --- ## [Upcoming ABC flow changes](https://yosyshq.discourse.group/t/upcoming-abc-flow-changes/133)
**Author:** [@lofty](https://yosyshq.discourse.group/u/lofty)\ **Replies:** 3\ **Last updated:** [April 21, 2026, 9:08am UTC](https://yosyshq.discourse.group/t/upcoming-abc-flow-changes/133 "2026-04-21T09:08:19Z")
Hello, I have been working on some big changes on the interface to ABC in Yosys and wish to inform others about them. Yosys presently has three different commands for running ABC: abc, abc9 and abc\_new. abc is the ori… --- ## [Verification of designs involving multiple clocks](https://yosyshq.discourse.group/t/verification-of-designs-involving-multiple-clocks/136)
**Author:** [@tcyu](https://yosyshq.discourse.group/u/tcyu)\ **Replies:** 2\ **Last updated:** [April 8, 2026, 12:29pm UTC](https://yosyshq.discourse.group/t/verification-of-designs-involving-multiple-clocks/136 "2026-04-08T12:29:01Z")
Hello! I’ve been using yosys to convert designs into AIGs for model checking with rIC3 for the past few weeks. Recently, I ecountered some weird counterexamples reported by the model checker. For these counterexamples, t… --- ## [Non-determinism with OpenROAD](https://yosyshq.discourse.group/t/non-determinism-with-openroad/132)
**Author:** [@gudeh](https://yosyshq.discourse.group/u/gudeh)\ **Replies:** 6\ **Last updated:** [March 27, 2026, 2:47pm UTC](https://yosyshq.discourse.group/t/non-determinism-with-openroad/132 "2026-03-27T14:47:02Z")
Hey there, there might a non-determinism happening with yosys. The following screenshots are from OpenROAD at the Yosys stage, both logs should have no differences among them. They come from a pair of runs with a no-op b… --- ## [Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)](https://yosyshq.discourse.group/t/yosys-0-61-21-up5k-48mhz-internal-clock-wont-build-no-pll/131)
**Author:** [@peepo](https://yosyshq.discourse.group/u/peepo)\ **Replies:** 2\ **Last updated:** [March 16, 2026, 6:04pm UTC](https://yosyshq.discourse.group/t/yosys-0-61-21-up5k-48mhz-internal-clock-wont-build-no-pll/131 "2026-03-16T18:04:00Z")
Using either no definition or 0b00 output states : ERROR: max frequency for clock is 46.6mhz (FAIL at 48:00 Mhz) is this a bug? is there a workaround? seems rather odd, this is very simple code. SB\_HFOSC u\_hfosc ( … --- ## [Getting 49.15 MHz clock from 3.072 MHz external clock](https://yosyshq.discourse.group/t/getting-49-15-mhz-clock-from-3-072-mhz-external-clock/130)
**Author:** [@flyingcog](https://yosyshq.discourse.group/u/flyingcog)\ **Replies:** 1\ **Last updated:** [March 9, 2026, 11:31am UTC](https://yosyshq.discourse.group/t/getting-49-15-mhz-clock-from-3-072-mhz-external-clock/130 "2026-03-09T11:31:12Z")
I have hard time understanding PLL as I don’t have experience with FPGA’s. I have 2.822 MHz external clock (I can control pin) and I want to derive 90.32 MHz clock so that they are in sync. icepll unfortunately says 3.0… --- ## [SRMODE = "CE\_OVER\_LSR" how to implement in Yosys?](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123)
**Author:** [@peepo](https://yosyshq.discourse.group/u/peepo)\ **Replies:** 17\ **Last updated:** [March 5, 2026, 5:29pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123 "2026-03-05T17:29:19Z")
FD1P3XZ my\_reg \[7:0\] { .D(), .SP(), .CK(), .SR(), .Q(), } regarding SR type latches I found: However, this did not provide immediate relief!! The above snippet builds (UP5K) on Lattice Radiant, under Yosys rep… --- ## [CXXRTL virtual interfaces](https://yosyshq.discourse.group/t/cxxrtl-virtual-interfaces/129)
**Author:** [@laugensalm](https://yosyshq.discourse.group/u/laugensalm)\ **Replies:** 0\ **Last updated:** [March 2, 2026, 11:57am UTC](https://yosyshq.discourse.group/t/cxxrtl-virtual-interfaces/129 "2026-03-02T11:57:23Z")
I”ve been using CXXRTL a few years now to create cycle accurate hardware mockups like with Verilator, in the process, a few virtual devices got ported over to CXXRTL blackboxes from a library that did the same virtualiza… --- ## [What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?](https://yosyshq.discourse.group/t/what-is-the-best-way-to-drive-yosys-cli-to-use-cxxrtl-from-rust/128)
**Author:** [@photon](https://yosyshq.discourse.group/u/photon)\ **Replies:** 4\ **Last updated:** [March 1, 2026, 3:05am UTC](https://yosyshq.discourse.group/t/what-is-the-best-way-to-drive-yosys-cli-to-use-cxxrtl-from-rust/128 "2026-03-01T03:05:05Z")
I maintain a library that exposes hardware designs in Rust backed by dynamically opening libraries generated by Verilator, and I am interested in adding CXXRTL as an alternate “backend”. I would like to produce a CXXRTL… --- ## [Src attribute preservation](https://yosyshq.discourse.group/t/src-attribute-preservation/126)
**Author:** [@robtaylor](https://yosyshq.discourse.group/u/robtaylor)\ **Replies:** 1\ **Last updated:** [February 26, 2026, 3:38pm UTC](https://yosyshq.discourse.group/t/src-attribute-preservation/126 "2026-02-26T15:38:00Z")
Following up on @Ravenslofty’s Add node retention tracking through ABC transformations by robtaylor · Pull Request #41 · YosysHQ/abc · GitHub - I’ve been looking into using the “y” XAIGER extension instead of adding new… [Next page](https://yosyshq.discourse.group/latest.md?page=1)