# Users **URL:** https://yosyshq.discourse.group/c/users/5.md [Latest](https://yosyshq.discourse.group/latest.md) · [Categories](https://yosyshq.discourse.group/categories.md) · [Tags](https://yosyshq.discourse.group/tags.md) --- ## [About the Users category](https://yosyshq.discourse.group/t/about-the-users-category/17)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 0\ **Last updated:** [March 20, 2025, 4:26pm UTC](https://yosyshq.discourse.group/t/about-the-users-category/17 "2025-03-20T16:26:56Z")
This space is for users of Yosys and other Yosys HQ tools. If you have questions about developing for Yosys or infrastructure which uses it, please use the Developers category. If you are unsure about something being a … --- ## [Is This a Forum where I Can Ask Questions about Verilog?](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156)
**Author:** [@kvnsmnsn](https://yosyshq.discourse.group/u/kvnsmnsn)\ **Replies:** 5\ **Last updated:** [September 1, 2026, 8:34am UTC](https://yosyshq.discourse.group/t/is-this-a-forum-where-i-can-ask-questions-about-verilog/156 "2026-09-01T08:34:23Z")
I’ve got a bit of Verilog code, and I’m wondering what it actually does, how it actually gets implemented. Is this a good forum to discuss that? If not, can someone point me to a forum that is more appropriate? --- ## [Sanity check: interpreting synth\_xilinx BRAM/LUT/FF counts in a memory-topology comparison](https://yosyshq.discourse.group/t/sanity-check-interpreting-synth-xilinx-bram-lut-ff-counts-in-a-memory-topology-comparison/159)
**Author:** [@AlexSafonov](https://yosyshq.discourse.group/u/AlexSafonov)\ **Replies:** 2\ **Last updated:** [August 28, 2026, 1:04pm UTC](https://yosyshq.discourse.group/t/sanity-check-interpreting-synth-xilinx-bram-lut-ff-counts-in-a-memory-topology-comparison/159 "2026-08-28T13:04:14Z")
Title: Sanity check: interpreting synth\_xilinx BRAM/LUT/FF counts in a memory-topology comparison Hi, I’m looking for a narrow Yosys methodology sanity check on PB-HW-04, a small structural comparison of four organizat… --- ## [An open-source high-level synthesis tool that accepts idiomatic Python](https://yosyshq.discourse.group/t/an-open-source-high-level-synthesis-tool-that-accepts-idiomatic-python/154)
**Author:** [@Pavel](https://yosyshq.discourse.group/u/Pavel)\ **Replies:** 4\ **Last updated:** [August 20, 2026, 9:37pm UTC](https://yosyshq.discourse.group/t/an-open-source-high-level-synthesis-tool-that-accepts-idiomatic-python/154 "2026-08-20T21:37:05Z")
Recently I’ve been working on a certain embedded system that has an FPGA running EKF and some controls. Coding that in RTL is inefficient at best so I turned to HLS and looked around to see what the industry has to offer… --- ## [Equiv\_opt on hierarchical designs](https://yosyshq.discourse.group/t/equiv-opt-on-hierarchical-designs/152)
**Author:** [@donn](https://yosyshq.discourse.group/u/donn)\ **Replies:** 1\ **Last updated:** [June 22, 2026, 10:32pm UTC](https://yosyshq.discourse.group/t/equiv-opt-on-hierarchical-designs/152 "2026-06-22T22:32:20Z")
One of the tests I’m debugging currently runs a pass on a design that happens to have a submodule: read\_verilog \<\ **Author:** [@tambewilliam](https://yosyshq.discourse.group/u/tambewilliam)\ **Replies:** 1\ **Last updated:** [May 20, 2026, 1:50pm UTC](https://yosyshq.discourse.group/t/why-is-synth-ecp5-flag-dff-not-enabled-by-default/150 "2026-05-20T13:50:31Z") My design appears to much easily meet timing when I use the synth\_ecp5 flag -dff, which run abc9 with -dff option. Is there a reason why it is not enabled by default ? Does it have drawbacks ? --- ## [Issue with Defining Power Pins in Standalone Yosys (USE\_POWER\_PINS not taking effect)](https://yosyshq.discourse.group/t/issue-with-defining-power-pins-in-standalone-yosys-use-power-pins-not-taking-effect/144)
**Author:** [@Vishal](https://yosyshq.discourse.group/u/Vishal)\ **Replies:** 1\ **Last updated:** [May 15, 2026, 5:19am UTC](https://yosyshq.discourse.group/t/issue-with-defining-power-pins-in-standalone-yosys-use-power-pins-not-taking-effect/144 "2026-05-15T05:19:17Z")
Hi I am using Standalone Yosys Version 0.62 for RTL synthesis. In my design, some modules include power pins conditionally using the following Verilog construct: ifdef USE\_POWER\_PINS .VPWR(vccd), .VGND(vssd… --- ## [timing closure degraded](https://yosyshq.discourse.group/t/timing-closure-degraded/139)
**Author:** [@tambewilliam](https://yosyshq.discourse.group/u/tambewilliam)\ **Replies:** 8\ **Last updated:** [May 13, 2026, 3:45pm UTC](https://yosyshq.discourse.group/t/timing-closure-degraded/139 "2026-05-13T15:45:46Z")
Between oss-cad-suite 20251204 (with nextpnr-0.9-43) and 20260415 (nextpnr-0.10-33), something changed such that nextpnr-ecp5, for the same exact design that used to pass 48 MHz timing, now fails achieving only 30 MHz. … --- ## [Verification of designs involving multiple clocks](https://yosyshq.discourse.group/t/verification-of-designs-involving-multiple-clocks/136)
**Author:** [@tcyu](https://yosyshq.discourse.group/u/tcyu)\ **Replies:** 2\ **Last updated:** [April 8, 2026, 12:29pm UTC](https://yosyshq.discourse.group/t/verification-of-designs-involving-multiple-clocks/136 "2026-04-08T12:29:01Z")
Hello! I’ve been using yosys to convert designs into AIGs for model checking with rIC3 for the past few weeks. Recently, I ecountered some weird counterexamples reported by the model checker. For these counterexamples, t… --- ## [Yosys 0.61+21 up5k 48mhz internal clock won't build (no PLL)](https://yosyshq.discourse.group/t/yosys-0-61-21-up5k-48mhz-internal-clock-wont-build-no-pll/131)
**Author:** [@peepo](https://yosyshq.discourse.group/u/peepo)\ **Replies:** 2\ **Last updated:** [March 16, 2026, 6:04pm UTC](https://yosyshq.discourse.group/t/yosys-0-61-21-up5k-48mhz-internal-clock-wont-build-no-pll/131 "2026-03-16T18:04:00Z")
Using either no definition or 0b00 output states : ERROR: max frequency for clock is 46.6mhz (FAIL at 48:00 Mhz) is this a bug? is there a workaround? seems rather odd, this is very simple code. SB\_HFOSC u\_hfosc ( … --- ## [Getting 49.15 MHz clock from 3.072 MHz external clock](https://yosyshq.discourse.group/t/getting-49-15-mhz-clock-from-3-072-mhz-external-clock/130)
**Author:** [@flyingcog](https://yosyshq.discourse.group/u/flyingcog)\ **Replies:** 1\ **Last updated:** [March 9, 2026, 11:31am UTC](https://yosyshq.discourse.group/t/getting-49-15-mhz-clock-from-3-072-mhz-external-clock/130 "2026-03-09T11:31:12Z")
I have hard time understanding PLL as I don’t have experience with FPGA’s. I have 2.822 MHz external clock (I can control pin) and I want to derive 90.32 MHz clock so that they are in sync. icepll unfortunately says 3.0… --- ## [SRMODE = "CE\_OVER\_LSR" how to implement in Yosys?](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123)
**Author:** [@peepo](https://yosyshq.discourse.group/u/peepo)\ **Replies:** 17\ **Last updated:** [March 5, 2026, 5:29pm UTC](https://yosyshq.discourse.group/t/srmode-ce-over-lsr-how-to-implement-in-yosys/123 "2026-03-05T17:29:19Z")
FD1P3XZ my\_reg \[7:0\] { .D(), .SP(), .CK(), .SR(), .Q(), } regarding SR type latches I found: However, this did not provide immediate relief!! The above snippet builds (UP5K) on Lattice Radiant, under Yosys rep… --- ## [CXXRTL virtual interfaces](https://yosyshq.discourse.group/t/cxxrtl-virtual-interfaces/129)
**Author:** [@laugensalm](https://yosyshq.discourse.group/u/laugensalm)\ **Replies:** 0\ **Last updated:** [March 2, 2026, 11:57am UTC](https://yosyshq.discourse.group/t/cxxrtl-virtual-interfaces/129 "2026-03-02T11:57:23Z")
I”ve been using CXXRTL a few years now to create cycle accurate hardware mockups like with Verilator, in the process, a few virtual devices got ported over to CXXRTL blackboxes from a library that did the same virtualiza… --- ## [What is the best way to drive Yosys CLI (to use CXXRTL) from Rust?](https://yosyshq.discourse.group/t/what-is-the-best-way-to-drive-yosys-cli-to-use-cxxrtl-from-rust/128)
**Author:** [@photon](https://yosyshq.discourse.group/u/photon)\ **Replies:** 4\ **Last updated:** [March 1, 2026, 3:05am UTC](https://yosyshq.discourse.group/t/what-is-the-best-way-to-drive-yosys-cli-to-use-cxxrtl-from-rust/128 "2026-03-01T03:05:05Z")
I maintain a library that exposes hardware designs in Rust backed by dynamically opening libraries generated by Verilator, and I am interested in adding CXXRTL as an alternate “backend”. I would like to produce a CXXRTL… --- ## [Async2sync and write\_aiger -vmap](https://yosyshq.discourse.group/t/async2sync-and-write-aiger-vmap/120)
**Author:** [@Truito](https://yosyshq.discourse.group/u/Truito)\ **Replies:** 2\ **Last updated:** [February 9, 2026, 1:04pm UTC](https://yosyshq.discourse.group/t/async2sync-and-write-aiger-vmap/120 "2026-02-09T13:04:18Z")
Hi, I am using async2sync command and write\_aiger with the vmap option on verilog netlists. The obtained mapping is as I would have expected. Except for the latches that comes from the async2sync pass. Where I got stuff… --- ## [How do you lint your Yosys Verilog projects?](https://yosyshq.discourse.group/t/how-do-you-lint-your-yosys-verilog-projects/117)
**Author:** [@zapta](https://yosyshq.discourse.group/u/zapta)\ **Replies:** 4\ **Last updated:** [January 26, 2026, 8:40pm UTC](https://yosyshq.discourse.group/t/how-do-you-lint-your-yosys-verilog-projects/117 "2026-01-26T20:40:59Z")
This is a continuation from the discussion here https://github.com/FPGAwars/apio/discussions . Yosys recommends linting with Verilator but when we do so we get from tons of warnings from Yosys standard libraries and wit… --- ## [Setundef doesn't respect selection](https://yosyshq.discourse.group/t/setundef-doesnt-respect-selection/114)
**Author:** [@mkudinov](https://yosyshq.discourse.group/u/mkudinov)\ **Replies:** 1\ **Last updated:** [January 21, 2026, 6:25pm UTC](https://yosyshq.discourse.group/t/setundef-doesnt-respect-selection/114 "2026-01-21T18:25:43Z")
I’m trying to apply setundef only to the part of my design, but seems like it doesn’t respect selection. For example: module test; wire a = 1'bx; wire b = 1'bx; endmodule After running setundef -zero w:a I ex… --- ## [Stopping to prevent exponential design size explosion](https://yosyshq.discourse.group/t/stopping-to-prevent-exponential-design-size-explosion/111)
**Author:** [@manish](https://yosyshq.discourse.group/u/manish)\ **Replies:** 2\ **Last updated:** [January 16, 2026, 3:31am UTC](https://yosyshq.discourse.group/t/stopping-to-prevent-exponential-design-size-explosion/111 "2026-01-16T03:31:23Z")
Hello, I was trying to compile a SystemVerilog design with Verific (with Tabby CAD license). This design works with Synopsys VCS. While compiling the design, I get the following error. Importing module cache\_controll… --- ## [SBY: liveness check (deadlock / livelock)](https://yosyshq.discourse.group/t/sby-liveness-check-deadlock-livelock/110)
**Author:** [@MysticExplorer](https://yosyshq.discourse.group/u/MysticExplorer)\ **Replies:** 2\ **Last updated:** [December 17, 2025, 9:30am UTC](https://yosyshq.discourse.group/t/sby-liveness-check-deadlock-livelock/110 "2025-12-17T09:30:18Z")
I’m evaluating SBY’s liveness checking. I created a simple FSM (module deadlock\_test) with an intentional deadlock: the ‘locked’ state should violate a deadlock check, and (at least) the initial idle state should violate… --- ## [Internal pins in Liberty files](https://yosyshq.discourse.group/t/internal-pins-in-liberty-files/107)
**Author:** [@taktoa](https://yosyshq.discourse.group/u/taktoa)\ **Replies:** 1\ **Last updated:** [December 9, 2025, 8:53pm UTC](https://yosyshq.discourse.group/t/internal-pins-in-liberty-files/107 "2025-12-09T20:53:44Z")
Currently, read\_liberty errors out on internal pins, which I believe should just be ignored. An example of this is the IQ pin in the ASAP7 ICG clock gate cells., where we get ERROR: Missing function on output IQ of cell… --- ## [Write\_json: buffer output after NOT gate left floating](https://yosyshq.discourse.group/t/write-json-buffer-output-after-not-gate-left-floating/104)
**Author:** [@nmendezst](https://yosyshq.discourse.group/u/nmendezst)\ **Replies:** 1\ **Last updated:** [November 19, 2025, 11:00pm UTC](https://yosyshq.discourse.group/t/write-json-buffer-output-after-not-gate-left-floating/104 "2025-11-19T23:00:51Z")
Hi. I was doing some experiments with yosys and netlistsvg to render a logic schematic from Verilog. I want to keep the buffers in the schematic, I’m using insbuf (is it the right approach?) and I came across this issue… --- ## [Yosys Formal : VCD Trace Dump](https://yosyshq.discourse.group/t/yosys-formal-vcd-trace-dump/102)
**Author:** [@dv\_coder](https://yosyshq.discourse.group/u/dv_coder)\ **Replies:** 3\ **Last updated:** [November 12, 2025, 8:11pm UTC](https://yosyshq.discourse.group/t/yosys-formal-vcd-trace-dump/102 "2025-11-12T20:11:47Z")
Hi, We are currently on an evaluation license of the Tabby CAD suite for formal. The VCD for a failing trace contains only a small set of signals making it harder to debug. Is there an option to dump specific signals/m… --- ## [Educational Uses of Open Source EDA Tools](https://yosyshq.discourse.group/t/educational-uses-of-open-source-eda-tools/100)
**Author:** [@bsiever](https://yosyshq.discourse.group/u/bsiever)\ **Replies:** 2\ **Last updated:** [November 4, 2025, 1:05pm UTC](https://yosyshq.discourse.group/t/educational-uses-of-open-source-eda-tools/100 "2025-11-04T13:05:56Z")
Apologies if this isn’t suitable for this forum. There are many of us using open EDA tools, like Yosys, in education and research. Collaboration on common concerns could benefit everyone. If anyone is interested in for… --- ## [Gate Count Instability from Functionally Equivalent RTL](https://yosyshq.discourse.group/t/gate-count-instability-from-functionally-equivalent-rtl/99)
**Author:** [@mnur](https://yosyshq.discourse.group/u/mnur)\ **Replies:** 1\ **Last updated:** [October 30, 2025, 8:18pm UTC](https://yosyshq.discourse.group/t/gate-count-instability-from-functionally-equivalent-rtl/99 "2025-10-30T20:18:58Z")
Hello Yosys team and community, I’m self-learning digital logic and I’m synthesizing a tiny CPU for nangate45. I’m observing significant instability in my synthesis results. Minor, functionally equivalent RTL changes ar… --- ## [Preserving RTL provenance (component context) through Yosys synthesis and AIG mapping](https://yosyshq.discourse.group/t/preserving-rtl-provenance-component-context-through-yosys-synthesis-and-aig-mapping/96)
**Author:** [@raulf2012](https://yosyshq.discourse.group/u/raulf2012)\ **Replies:** 2\ **Last updated:** [October 10, 2025, 5:16pm UTC](https://yosyshq.discourse.group/t/preserving-rtl-provenance-component-context-through-yosys-synthesis-and-aig-mapping/96 "2025-10-10T17:16:46Z")
Hello everyone, Edit: I am using version 0.33, installed via apt install (Ubuntu/WSL). I’m working on a project that uses Yosys to analyze synthesized circuits. I’m taking RTL designs (in my case, a parameterized FIR f… --- ## [Correct method to ignore assert() statements?](https://yosyshq.discourse.group/t/correct-method-to-ignore-assert-statements/84)
**Author:** [@dlmiles](https://yosyshq.discourse.group/u/dlmiles)\ **Replies:** 2\ **Last updated:** [October 6, 2025, 9:43pm UTC](https://yosyshq.discourse.group/t/correct-method-to-ignore-assert-statements/84 "2025-10-06T21:43:42Z")
Hello, During a production synthesis run, intended to target a physical design (in this case ASIC), as opposed Formal Verification, Simulation, Design-For-Test and other non-production use cases. When using hierarchy -… --- ## [Seq #("xx\_\_\_\_x\_\_\_\_\_\_\_\_\_\_\_\_\_") pkt\_err (clk, packet\_error);](https://yosyshq.discourse.group/t/seq-xx-x-pkt-err-clk-packet-error/85)
**Author:** [@TomV](https://yosyshq.discourse.group/u/TomV)\ **Replies:** 1\ **Last updated:** [September 28, 2025, 6:12pm UTC](https://yosyshq.discourse.group/t/seq-xx-x-pkt-err-clk-packet-error/85 "2025-09-28T18:12:45Z")
In application note 109, there are snippets such as this one: default clocking @(posedge clk); endclocking default disable iff(!rstn); seq #("\_\_------------------") reset (clk, rstn); seq #("xx\_\_\_\_x\_\_\_\_\_\_\_\_\_… --- ## [Incremental Synthesis in Yosys](https://yosyshq.discourse.group/t/incremental-synthesis-in-yosys/80)
**Author:** [@mark\_sys](https://yosyshq.discourse.group/u/mark_sys)\ **Replies:** 4\ **Last updated:** [September 9, 2025, 4:24am UTC](https://yosyshq.discourse.group/t/incremental-synthesis-in-yosys/80 "2025-09-09T04:24:02Z")
I see vivado and altera supports incremental synthesis in their flow vivado has DCP(Design checkpoints ) that will be used while re-synthesizing and users base mention that it is effective when there is change of atmos… --- ## [SystemVerilog 2012 Parsing for RVFI](https://yosyshq.discourse.group/t/systemverilog-2012-parsing-for-rvfi/73)
**Author:** [@cherry-bunny779](https://yosyshq.discourse.group/u/cherry-bunny779)\ **Replies:** 1\ **Last updated:** [August 31, 2025, 10:57pm UTC](https://yosyshq.discourse.group/t/systemverilog-2012-parsing-for-rvfi/73 "2025-08-31T22:57:32Z")
Hello, I am having a similar issue with an earlier post with the title “Support for package import (unexpected TOK\_ID)”. Except that I am attempting to run the RVFI verification flow on the cv32e40x processor, and the r… --- ## [Larger N for input but less time used](https://yosyshq.discourse.group/t/larger-n-for-input-but-less-time-used/63)
**Author:** [@MMMMMia](https://yosyshq.discourse.group/u/MMMMMia)\ **Replies:** 4\ **Last updated:** [August 28, 2025, 6:50pm UTC](https://yosyshq.discourse.group/t/larger-n-for-input-but-less-time-used/63 "2025-08-28T18:50:45Z")
Hi everyone, I came across something quite interesting while verifying two adders using EQY. I observed that when N=7168, which is larger than N=7040, the verification time dropped significantly instead of increasing. I… [Next page](https://yosyshq.discourse.group/c/users/5.md?page=1)