# Developers **URL:** https://yosyshq.discourse.group/c/developers/6.md [Latest](https://yosyshq.discourse.group/latest.md) · [Categories](https://yosyshq.discourse.group/categories.md) · [Tags](https://yosyshq.discourse.group/tags.md) --- ## [About the Developers category](https://yosyshq.discourse.group/t/about-the-developers-category/18)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 0\ **Last updated:** [March 20, 2025, 4:28pm UTC](https://yosyshq.discourse.group/t/about-the-developers-category/18 "2025-03-20T16:28:54Z")
This space is for contributors and downstream development users of Yosys and other Yosys HQ tools, including academic tooling development. If you’re using these tools for design and verification without modifying them, p… --- ## [Adding a pass for Multiple Constant Multiplication (mcm)](https://yosyshq.discourse.group/t/adding-a-pass-for-multiple-constant-multiplication-mcm/165)
**Author:** [@hfthra](https://yosyshq.discourse.group/u/hfthra)\ **Replies:** 6\ **Last updated:** [September 21, 2026, 12:31pm UTC](https://yosyshq.discourse.group/t/adding-a-pass-for-multiple-constant-multiplication-mcm/165 "2026-09-21T12:31:10Z")
I am creating a new pass for restructuring multiplication with constants into shifts with addition/subtraction. $mul operations with constants will be implemented as shifts, which results in a smaller mapped area than im… --- ## [Reverse-engineering Renesas ForgeFPGA SLG47910V for open-source Yosys/FPGA support](https://yosyshq.discourse.group/t/reverse-engineering-renesas-forgefpga-slg47910v-for-open-source-yosys-fpga-support/168)
**Author:** [@Aasssink786](https://yosyshq.discourse.group/u/Aasssink786)\ **Replies:** 0\ **Last updated:** [September 11, 2026, 8:47pm UTC](https://yosyshq.discourse.group/t/reverse-engineering-renesas-forgefpga-slg47910v-for-open-source-yosys-fpga-support/168 "2026-09-11T20:47:04Z")
Hi YosysHQ team, I’m currently working on reverse-engineering the Renesas ForgeFPGA SLG47910V architecture, used by the Vicharak Shrike family, with the goal of enabling a more open-source FPGA toolchain. I’m starting … --- ## [Interim LLM Policy](https://yosyshq.discourse.group/t/interim-llm-policy/163)
**Author:** [@Kate\_Yosys](https://yosyshq.discourse.group/u/Kate_Yosys)\ **Replies:** 0\ **Last updated:** [August 31, 2026, 1:49pm UTC](https://yosyshq.discourse.group/t/interim-llm-policy/163 "2026-08-31T13:49:10Z")
As the maintainers of OSS CAD suite and Tabby CAD suite, we’ve seen an increasing number of pull requests containing LLM generated code. Developing a consistent and unanimously accepted approach on how we intend to handl… --- ## [Your CMake workflows](https://yosyshq.discourse.group/t/your-cmake-workflows/155)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 1\ **Last updated:** [July 23, 2026, 9:22pm UTC](https://yosyshq.discourse.group/t/your-cmake-workflows/155 "2026-07-23T21:22:30Z")
Since we switched Yosys to CMake, I wanted as simple a workflow as before. Thankfully user presets are super convenient. Here’s my presets file: With this I can do, for example, cmake --workflow --preset d to configure… --- ## [Adding support for LATCH mapping to \`dfflibmap\`](https://yosyshq.discourse.group/t/adding-support-for-latch-mapping-to-dfflibmap/153)
**Author:** [@iztok.jeras](https://yosyshq.discourse.group/u/iztok.jeras)\ **Replies:** 1\ **Last updated:** [June 22, 2026, 4:30pm UTC](https://yosyshq.discourse.group/t/adding-support-for-latch-mapping-to-dfflibmap/153 "2026-06-22T16:30:38Z")
I created a \[pull request\]( Update to \`dfflibmap\` to be able to map LATCHes by jeras · Pull Request #5976 · YosysHQ/yosys · GitHub ) draft which adds support for mapping LATCHes from a SCL Liberty file. The code is build… --- ## [Consistent source location transfer with Patch](https://yosyshq.discourse.group/t/consistent-source-location-transfer-with-patch/121)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 3\ **Last updated:** [June 11, 2026, 10:57am UTC](https://yosyshq.discourse.group/t/consistent-source-location-transfer-with-patch/121 "2026-06-11T10:57:57Z")
The greatest source of loss of source attributes is synthesis with abc, but not all users use abc and there’s a lot of gaps in Yosys passes. To address this, there’s two major features I think we need. Patch I have star… --- ## [Fixing \`IdString\` refcounting](https://yosyshq.discourse.group/t/fixing-idstring-refcounting/94)
**Author:** [@rocallahan](https://yosyshq.discourse.group/u/rocallahan)\ **Replies:** 11\ **Last updated:** [June 11, 2026, 6:36am UTC](https://yosyshq.discourse.group/t/fixing-idstring-refcounting/94 "2026-06-11T06:36:12Z")
IdString refcounting adds overhead and code bloat, and would be even more overhead if we try to make it make safe for multithreading, so it would be good to remove most or all of it. Instead of refcounting, we could try… --- ## [An update on C++-ification of logging APIs](https://yosyshq.discourse.group/t/an-update-on-c-ification-of-logging-apis/77)
**Author:** [@rocallahan](https://yosyshq.discourse.group/u/rocallahan)\ **Replies:** 5\ **Last updated:** [June 9, 2026, 5:56pm UTC](https://yosyshq.discourse.group/t/an-update-on-c-ification-of-logging-apis/77 "2026-06-09T17:56:49Z")
Until recently the Yosys stringf() and logging APIs used C-style variadic functions. That means C++ objects like std::string and std::string\_view can’t be passed directly, so the code is littered with .c\_str() calls… and… --- ## [Poll: LLMs - quality, morality, opportunity, policy](https://yosyshq.discourse.group/t/poll-llms-quality-morality-opportunity-policy/151)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 2\ **Last updated:** [May 29, 2026, 6:21pm UTC](https://yosyshq.discourse.group/t/poll-llms-quality-morality-opportunity-policy/151 "2026-05-29T18:21:04Z")
LLM contributions to Yosys are on the rise and we are considering adding LLM-specific rules to contribution guidelines. We’ve had brief discussions of the applicability of LLM coding tools internally, and I would like to… --- ## [Proving the prover, or "How do we verify we're constructing SVA assertions correctly?"](https://yosyshq.discourse.group/t/proving-the-prover-or-how-do-we-verify-were-constructing-sva-assertions-correctly/148)
**Author:** [@melyoung](https://yosyshq.discourse.group/u/melyoung)\ **Replies:** 3\ **Last updated:** [May 29, 2026, 4:01pm UTC](https://yosyshq.discourse.group/t/proving-the-prover-or-how-do-we-verify-were-constructing-sva-assertions-correctly/148 "2026-05-29T16:01:58Z")
Heya everyone, I’m working with povik and some other contributors (namely mndstrmr) to yosys-slang to add better support for SVA assertions over there (Rebase SVA support into main by mlyoung101 · Pull Request #317 · po… --- ## [RFC: Announcing the new intermediate representation Property IR for assertions (SVA/PSL)](https://yosyshq.discourse.group/t/rfc-announcing-the-new-intermediate-representation-property-ir-for-assertions-sva-psl/143)
**Author:** [@lena](https://yosyshq.discourse.group/u/lena)\ **Replies:** 4\ **Last updated:** [May 18, 2026, 4:13am UTC](https://yosyshq.discourse.group/t/rfc-announcing-the-new-intermediate-representation-property-ir-for-assertions-sva-psl/143 "2026-05-18T04:13:05Z")
Property IR is a new intermediate representation for temporal properties as specified by SystemVerilog Assertions (SVA). The goal is to support formal verification flows, while decoupling front-end tasks (parsing, name r… --- ## [Itp engine: fixpoint convergence and skip parameter](https://yosyshq.discourse.group/t/itp-engine-fixpoint-convergence-and-skip-parameter/149)
**Author:** [@inquisitour](https://yosyshq.discourse.group/u/inquisitour)\ **Replies:** 0\ **Last updated:** [May 15, 2026, 10:17pm UTC](https://yosyshq.discourse.group/t/itp-engine-fixpoint-convergence-and-skip-parameter/149 "2026-05-15T22:17:11Z")
Hello everyone, During benchmarking on riscv-formal cores (NERV, PicoRV32, SERV, VexRiscv) with the itp engine, I found fixpoint convergence works correctly with skip=0 but returns bounded results only when skip\>0. The … --- ## [SDC support roadmap](https://yosyshq.discourse.group/t/sdc-support-roadmap/95)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 4\ **Last updated:** [May 7, 2026, 2:39pm UTC](https://yosyshq.discourse.group/t/sdc-support-roadmap/95 "2026-05-07T14:39:51Z")
There are several good reasons for Yosys to support various use cases that involve SDC. These use cases can be implemented in various ways. Here are my notes on the topic with some updates on how we’re going about to kic… --- ## [New PR with up to 2.57x performance improvements](https://yosyshq.discourse.group/t/new-pr-with-up-to-2-57x-performance-improvements/142)
**Author:** [@crockpotveggies](https://yosyshq.discourse.group/u/crockpotveggies)\ **Replies:** 3\ **Last updated:** [April 27, 2026, 8:33pm UTC](https://yosyshq.discourse.group/t/new-pr-with-up-to-2-57x-performance-improvements/142 "2026-04-27T20:33:16Z")
(numbers based on benchmarks and YMMV) I’ve opened a PR with some perf enhancements which I think will make a significant difference in speeding up some aspects of synthesis. I’ve sync’d with main and all tests appear t… --- ## [Upcoming ABC flow changes](https://yosyshq.discourse.group/t/upcoming-abc-flow-changes/133)
**Author:** [@lofty](https://yosyshq.discourse.group/u/lofty)\ **Replies:** 3\ **Last updated:** [April 21, 2026, 9:08am UTC](https://yosyshq.discourse.group/t/upcoming-abc-flow-changes/133 "2026-04-21T09:08:19Z")
Hello, I have been working on some big changes on the interface to ABC in Yosys and wish to inform others about them. Yosys presently has three different commands for running ABC: abc, abc9 and abc\_new. abc is the ori… --- ## [Non-determinism with OpenROAD](https://yosyshq.discourse.group/t/non-determinism-with-openroad/132)
**Author:** [@gudeh](https://yosyshq.discourse.group/u/gudeh)\ **Replies:** 6\ **Last updated:** [March 27, 2026, 2:47pm UTC](https://yosyshq.discourse.group/t/non-determinism-with-openroad/132 "2026-03-27T14:47:02Z")
Hey there, there might a non-determinism happening with yosys. The following screenshots are from OpenROAD at the Yosys stage, both logs should have no differences among them. They come from a pair of runs with a no-op b… --- ## [Src attribute preservation](https://yosyshq.discourse.group/t/src-attribute-preservation/126)
**Author:** [@robtaylor](https://yosyshq.discourse.group/u/robtaylor)\ **Replies:** 1\ **Last updated:** [February 26, 2026, 3:38pm UTC](https://yosyshq.discourse.group/t/src-attribute-preservation/126 "2026-02-26T15:38:00Z")
Following up on @Ravenslofty’s Add node retention tracking through ABC transformations by robtaylor · Pull Request #41 · YosysHQ/abc · GitHub - I’ve been looking into using the “y” XAIGER extension instead of adding new… --- ## [Default branch changes for nextpnr, icestorm, prjtrellis and prjoxide](https://yosyshq.discourse.group/t/default-branch-changes-for-nextpnr-icestorm-prjtrellis-and-prjoxide/125)
**Author:** [@gatecat](https://yosyshq.discourse.group/u/gatecat)\ **Replies:** 0\ **Last updated:** [February 26, 2026, 2:46pm UTC](https://yosyshq.discourse.group/t/default-branch-changes-for-nextpnr-icestorm-prjtrellis-and-prjoxide/125 "2026-02-26T14:46:41Z")
Just a heads up for packagers that the default branch for nextpnr, icestorm, prjtrellis and prjoxide has now been renamed to main --- ## [Big ideas for the future of Yosys](https://yosyshq.discourse.group/t/big-ideas-for-the-future-of-yosys/124)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 0\ **Last updated:** [February 20, 2026, 4:24pm UTC](https://yosyshq.discourse.group/t/big-ideas-for-the-future-of-yosys/124 "2026-02-20T16:24:48Z")
For bigger long-term technical ideas at Yosys HQ, for a long time now, we’ve been having sporadic meetings called “galaxy brain”. We’re publishing the document with potential topics and minutes to build yosys more “in th… --- ## [RFC: SVA / PSL implementation ideas](https://yosyshq.discourse.group/t/rfc-sva-psl-implementation-ideas/116)
**Author:** [@jjjt](https://yosyshq.discourse.group/u/jjjt)\ **Replies:** 3\ **Last updated:** [February 10, 2026, 2:15pm UTC](https://yosyshq.discourse.group/t/rfc-sva-psl-implementation-ideas/116 "2026-02-10T14:15:24Z")
Hey there, I find myself with some motivation to implement support for synthesis of temporal logics (e.g. SVA/PSL), at the beginning focusing on FV uses. The algorithm I have selected after some research is the one pro… --- ## [\[Proposal\] Automatic test for Yosys cell libraries?](https://yosyshq.discourse.group/t/proposal-automatic-test-for-yosys-cell-libraries/118)
**Author:** [@zapta](https://yosyshq.discourse.group/u/zapta)\ **Replies:** 2\ **Last updated:** [January 26, 2026, 10:43pm UTC](https://yosyshq.discourse.group/t/proposal-automatic-test-for-yosys-cell-libraries/118 "2026-01-26T22:43:53Z")
Background: Yosys recommends linting projects with Verilator and the oss-cad-suite package includes a Verilator binary. https://github.com/YosysHQ/yosys/blob/main/README.md#additional-information Yosys standard librari… --- ## [RFC: Upstreaming a small set of Verific frontend options from silimate fork](https://yosyshq.discourse.group/t/rfc-upstreaming-a-small-set-of-verific-frontend-options-from-silimate-fork/113)
**Author:** [@dhvll](https://yosyshq.discourse.group/u/dhvll)\ **Replies:** 4\ **Last updated:** [January 20, 2026, 10:40am UTC](https://yosyshq.discourse.group/t/rfc-upstreaming-a-small-set-of-verific-frontend-options-from-silimate-fork/113 "2026-01-20T10:40:35Z")
Hi, I’m working on upstreaming a small set of Verific-related frontend options that already exist in a downstream fork and are used to control Verific elaboration behavior. The changes are intentionally scoped and in… --- ## [Flops with parametrized ALOAD aren't optimized and synthesis fails](https://yosyshq.discourse.group/t/flops-with-parametrized-aload-arent-optimized-and-synthesis-fails/112)
**Author:** [@devsaurus](https://yosyshq.discourse.group/u/devsaurus)\ **Replies:** 5\ **Last updated:** [January 6, 2026, 11:41pm UTC](https://yosyshq.discourse.group/t/flops-with-parametrized-aload-arent-optimized-and-synthesis-fails/112 "2026-01-06T23:41:15Z")
It seems that the existing dff optimizations don’t detect when ALOAD and AD inputs are driven from the same or complementary signals. This prevents synthesis of designs that contain dffs with parametrized asynchronous re… --- ## [Sanitizing by default](https://yosyshq.discourse.group/t/sanitizing-by-default/109)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 0\ **Last updated:** [December 12, 2025, 3:22pm UTC](https://yosyshq.discourse.group/t/sanitizing-by-default/109 "2025-12-12T15:22:54Z")
Quick report: I tried enabling ubsan (SANITIZER=undefined) by default for debug builds of yosys, but when checking the clean build time, it turned out it increased from 64 to 100 seconds on my system, so I no longer want… --- ## [RTLIL and Verilog producers and consumers expectations for scopename and hdlname](https://yosyshq.discourse.group/t/rtlil-and-verilog-producers-and-consumers-expectations-for-scopename-and-hdlname/106)
**Author:** [@widlarizer](https://yosyshq.discourse.group/u/widlarizer)\ **Replies:** 1\ **Last updated:** [November 29, 2025, 1:06pm UTC](https://yosyshq.discourse.group/t/rtlil-and-verilog-producers-and-consumers-expectations-for-scopename-and-hdlname/106 "2025-11-29T13:06:29Z")
It’s come up that scopename and hdlname can have redundant information. Before we attempt to resolve this as part of better attribute preservation, since that might involve some level of redundance reduction, it would be… --- ## [Multithreading and coverage counters: disable coverage by default?](https://yosyshq.discourse.group/t/multithreading-and-coverage-counters-disable-coverage-by-default/105)
**Author:** [@rocallahan](https://yosyshq.discourse.group/u/rocallahan)\ **Replies:** 2\ **Last updated:** [November 26, 2025, 1:31pm UTC](https://yosyshq.discourse.group/t/multithreading-and-coverage-counters-disable-coverage-by-default/105 "2025-11-26T13:31:51Z")
Coverage counters currently aren’t thread-safe but that’s easily fixed. However, they significantly hurt performance when multithreading with large numbers of cores. For my parallel opt\_merge pass doing multithreaded re… --- ## [Handling non-const pointer fields and pointer-like structure fields when making const RTLIL objects thread-safe](https://yosyshq.discourse.group/t/handling-non-const-pointer-fields-and-pointer-like-structure-fields-when-making-const-rtlil-objects-thread-safe/103)
**Author:** [@rocallahan](https://yosyshq.discourse.group/u/rocallahan)\ **Replies:** 0\ **Last updated:** [November 10, 2025, 4:24am UTC](https://yosyshq.discourse.group/t/handling-non-const-pointer-fields-and-pointer-like-structure-fields-when-making-const-rtlil-objects-thread-safe/103 "2025-11-10T04:24:35Z")
See Parallel OptMergePass implementation for context. For maintainable multuthreaded read-only access to RTLIL, it would be extremely desirable for code that only has const references to RTLIL objects to be unable to mu… --- ## [Replacing json11?](https://yosyshq.discourse.group/t/replacing-json11/101)
**Author:** [@donn](https://yosyshq.discourse.group/u/donn)\ **Replies:** 1\ **Last updated:** [November 7, 2025, 11:38pm UTC](https://yosyshq.discourse.group/t/replacing-json11/101 "2025-11-07T23:38:54Z")
Hiya- I’ve recently struggled to write a pass that consumes JSON output from GitHub - Silimate/liberty2json: Liberty to JSON converter as part of contract work. Because Yosys already uses json11, I elected to just use t… --- ## [Adding gmock to test dependencies](https://yosyshq.discourse.group/t/adding-gmock-to-test-dependencies/98)
**Author:** [@Logikable](https://yosyshq.discourse.group/u/Logikable)\ **Replies:** 3\ **Last updated:** [November 1, 2025, 3:36am UTC](https://yosyshq.discourse.group/t/adding-gmock-to-test-dependencies/98 "2025-11-01T03:36:53Z")
Googlemock is a C++ testing library that is tightly coupled with Googletest. It augments gtest with a large suite of useful matchers; most of Matchers Reference | GoogleTest comes from gmock. I’d like to add it to .gith… [Next page](https://yosyshq.discourse.group/c/developers/6.md?page=1)